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부품번호 ISL26132 기능
기능 (ISL26132 / ISL26134) Low-Noise 24-bit Delta Sigma ADC
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ISL26132 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
Low-Noise 24-bit Delta Sigma ADC
ISL26132, ISL26134
The ISL26132 and ISL26134 are complete analog front ends
for high resolution measurement applications. These 24-bit
Delta-Sigma Analog-to-Digital Converters include a very
low-noise amplifier and are available as either two or four
differential multiplexer inputs. The devices offer the same
pinout as the ADS1232 and ADS1234 devices and are
functionally compatible with these devices. The ISL26132 and
ISL26134 offer improved noise performance at 10Sps and
80Sps conversion rates.
The on-chip low-noise programmable-gain amplifier provides
gains of 1x/2x/64x/128x. The 128x gain setting provides an
input range of ±9.766mVFS when using a 2.5V reference. The
high input impedance allows direct connection of sensors such
as load cell bridges to ensure the specified measurement
accuracy without additional circuitry. The inputs accept signals
100mV outside the supply rails when the device is set for unity
gain.
The Delta-Sigma ADC features a third order modulator
providing up to 21.6-bit noise-free performance.
The device can be operated from an external clock source,
crystal (4.9152MHz typical), or the on-chip oscillator.
The two channel ISL26132 is available in a 24 Ld TSSOP
package and the four channel ISL26134 is available in a 28 Ld
TSSOP package. Both are specified for operation over the
automotive temperature range (-40°C to +105°C).
Features
• Up to 21.6 Noise-free bits.
• Low Noise Amplifier with Gains of 1x/2x/64x/128x
• RMS noise: 10.2nV @ 10Sps (PGA = 128x)
• Linearity Error: 0.0002% FS
• Simultaneous rejection of 50Hz and 60Hz (@ 10Sps)
• Two (ISL26132) or four (ISL26134) channel differential
input multiplexer
• On-chip temperature sensor (ISL26132)
• Automatic clock source detection
• Simple interface to read conversions
• +5V Analog, +5 to +2.7V Digital Supplies
• Pb-Free (RoHS Compliant)
• TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin
Applications
• Weigh Scales
• Temperature Monitors and Controls
• Industrial Process Control
• Pressure Sensors
AVDD
CAP
DVDD
INTERNAL
CLOCK
EXTERNAL
OSCILLATOR
XTALIN/CLOCK
XTALOUT
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
ISL26134
Only AIN4+
AIN4-
INPUT
MULTIPLEXER
PGA
1x/2x/64x/
128x
ADC
SDO/RDY
SCLK
PWDN
SPEED
A0 A1/TEMP AGND GAIN0 GAIN1
CAP DGND
VREF+
VREF-
NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132
FIGURE 1. BLOCK DIAGRAM
DGND DGND
September 9, 2011
FN6954.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/




ISL26132 pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
ISL26132, ISL26134
Pin Descriptions (Continued)
NAME
SPEED
PIN NUMBER
ISL26132
ISL26134
21 25
ANALOG/DIGITAL
INPUT/OUTPUT
Digital Input
DESCRIPTION
TABLE 4. DATA RATE SELECT
SPEED
DATA RATE
0 10Sps
1 80Sps
PDWN
SCLK
SDO/RDY
22
23
24
26 Digital Input
27 Digital Input
28 Digital Output
Circuit Description
The ISL26132 (2-channel) and ISL26134 (4-channel) devices are
very low noise 24-bit delta-sigma ADCs that include a
programmable gain amplifier and an input multiplexer. The
ISL26132 offers an on-chip temperature measurement
capability.
The ISL26132, ISL26134 provide pin compatibility and output
data compatibility with the ADS1232/ADS1234, and offer the
same conversion rates of 10Sps and 80Sps.
All the features of the ISL26132, ISL26134 are pin-controllable,
while offset calibration, standby mode, and output conversion
data are accessible through a simple 2-wire interface.
The clock can be selected to come from an internal oscillator, an
external clock signal, or crystal (4.9152MHz typical).
Power-Down: Holding this pin low powers down the entire
converter and resets the ADC.
Serial Clock: Clock out data on the rising edge. Also used to
initiate Offset Calibration and Sleep modes. See “Serial Clock
Input (SCLK)” on page 14 for more details.
Dual-Purpose Output:
Data Ready: Indicate valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge
of SCLK.
4 FN6954.1
September 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/

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ISL26132 전자부품, 판매, 대치품
www.DataSheet.co.kr
ISL26132, ISL26134
Noise Performance
The ISL26132 and ISL26134 provide excellent noise
performance. The noise performance on each of the gain
settings of the PGA at the selected word rates is shown in
Tables 5 and 6.
Resolution in bits decreases by 1-bit if the ADC is operated as a
single-ended input device. Noise measurements are
input-referred, taken with bipolar inputs under the specified
operating conditions, with fCLK = 4.9152MHz.
TABLE 5. AVDD = 5V, VREF = 5V, DATA RATE = 10Sps
RMS NOISE
GAIN
(nV)
PEAK-TO-PEAK NOISE
(nV) (Note 10)
NOISE-FREE BITS
(Note 11)
1 243
1604
21.6
2 148
977
21.3
64 10.8
71
20.1
128 10.2
67
19.1
TABLE 6. AVDD = 5V, VREF = 5V, DATA RATE = 80Sps
GAIN
RMS NOISE PEAK-TO-PEAK NOISE NOISE-FREE BITS
(nV) (nV) (Note 10) (Note 11)
1 565
3730
20.4
2 285
1880
20.3
64 28.3
187
18.7
128 27
178
17.7
NOTES:
10. The peak-to-peak noise number is 6.6 times the rms value. This
encompasses 99.99% of the noise excursions that may occur. This
value best represents the worst case noise that could occur in the
output conversion words from the converter.
11. Noise-Free Bits is defined as: Noise-Free Bits = ln(FSR/peak-to-peak
noise)/ln(2) where FSR is the full scale range of the converter,
VREF/Gain.
7 FN6954.1
September 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/

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부품번호상세설명 및 기능제조사
ISL26132

(ISL26132 / ISL26134) Low-Noise 24-bit Delta Sigma ADC

Intersil
Intersil
ISL26134

(ISL26132 / ISL26134) Low-Noise 24-bit Delta Sigma ADC

Intersil
Intersil

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