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PDF ISL267450A Data sheet ( Hoja de datos )
| Número de pieza | ISL267450A | |
| Descripción | (ISL267440 / ISL267450A) 1MSPS SAR ADCs | |
| Fabricantes | Intersil | |
| Logotipo |  |
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10-Bit and 12-Bit, 1MSPS SAR ADCs
ISL267440, ISL267450A
The ISL267440 and ISL267450A are 10-bit and 12-bit, 1MSPS
sampling SAR-type ADCs featuring excellent linearity over supply
and temperature variations, which are drop-in compatible with
the AD7440 and AD7450A. The robust, fully-differential input
offers high impedance to minimize errors due to leakage
currents, and the specified measurement accuracy is maintained
with input signals up to the supply rails.
The reference accepts inputs from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation, which provides design
flexibility in a wide variety of applications. The ISL267440,
ISL267450A also feature up to 8kV Human Body Model ESD
survivability.
The serial digital interface is SPI compatible and is easily
interfaced to all popular FPGAs and microcontrollers. Power
dissipation is 8.5mW at a sampling rate of 1MSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 5V
supply), making the ISL267440, ISL267450A excellent solutions
for remote industrial sensors and battery-powered instruments.
The ISL267440, ISL267450A are available in an 8 lead MSOP
package, and are specified for operation over the Industrial
temperature range (–40°C to +85°C).
Features
• Drop-in Compatible with AD7440, AD7450A
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 1MHz Sampling Rate
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 1MSPS with 3V Supplies
- 1.70mA at 1MSPS with 5V Supplies
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in MSOP Package
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
VREF
VDD
VIN+
VIN–
SAR
LOGIC
SERIAL
INTERFACE
SCLK
SDATA
CS
VREF
GND
FIGURE 1. BLOCK DIAGRAM
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
1024
2048
CODE
3072
4096
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
December 5, 2011
FN7708.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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ISL267440, ISL267450A
Absolute Maximum Ratings
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld MSOP Package (Notes 5, 6). . . . . . . . .
165
64
8 Ld SOT-23 Package (Notes 5, 6). . . . . . . .
135
99
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 18MHz,
fS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
ISL267440
ISL267450A
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX MIN MAX
(Note 7) TYP (Note 7) (Note 7) TYP (Note 7) UNITS
DYNAMIC PERFORMANCE
SINAD
THD
SFDR
IMD
Signal-to (Noise + Distortion) Ratio fIN = 100kHz
VDD = +4.75V to +5.25V
fIN = 100kHz
VDD = +3.0V to +3.6V
Total Harmonic
Distortion
fIN = 100kHz
VDD = +4.75V to +5.25V
fIN = 100kHz
VDD = +3.0V to +3.6V
Spurious Free Dynamic Range
fIN = 100kHz
VDD = +4.75V to +5.25V
fIN = 100kHz
VDD = +3.0V to +3.6V
Intermodulation Distortion
2nd and 3rd order, fIN = 90kHz,
110kHz
61.0 61.6
70.0 71.4
dB
60.7 61.5
68.5 70.5
-82 -74
-84 -76 dB
-80 -72
-84 -74 dB
-82 -76
-87 -76 dB
-82 -74
-85 -74 dB
-92 -95 dB
tpd Aperture Delay
1 1 ns
Δtpd Aperture Jitter
15 15 ps
β3dB Full Power Bandwidth
@ –3dB
15 15 MHz
DC ACCURACY
N Resolution
10 12 Bits
INL Integral Nonlinearity
-0.5 ±0.1 0.5 -1 ±0.4 1 LSB
DNL Differential Nonlinearity
Guaranteed no missed codes to
12 bits (ISL267450A) or 10 bits
(ISL267440)
-0.5 ±0.1 0.5 -0.95 ±0.3 0.95 LSB
OFFSET Zero-Code Error
Zero Volt Differential Input
-2.5 ±0.2 2.5 -6 ±0.2 6 LSB
Positive Gain Error
GAIN
Negative Gain Error
± REF input range
-1 ±0.1 1 -2 ±0.1 2 LSB
-1 ±0.1 1 -2 ±0.1 2
ANALOG INPUT (Note 8)
|AIN| Full-Scale Input Span
2 x VREF
VIN+ - VIN–
VIN+ - VIN–
V
5 FN7708.0
December 5, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
ISL267440, ISL267450A
Functional Description
The ISL267440, ISL267450A are based on a successive
approximation register (SAR) architecture utilizing capacitive
charge redistribution digital to analog converters (DACs).
Figure 21 shows a simplified representation of the converter.
During the acquisition phase (ACQ) the differential input is stored
on the sampling capacitors (CS). The comparator is in a balanced
state since the switch across its inputs is closed. The signal is
fully acquired after tACQ has elapsed, and the switches then
transition to the conversion phase (CONV) so the stored voltage
may be converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
VIN+
VIN–
CONV CS
ACQ
ACQ
ACQ CONV
CONV CS
VREF
SAR
LOGIC
011...111
011...110
1LSB = 2 x REF/4096
000...001
000...000
111...111
100...010
100...001
100...000
-REF + 1LSB
0LSB +REF - 1LSB
ANALOG INPUT
(VIN+ – VIN-)
FIGURE 22. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267440, ISL267450A feature a fully differential input
with a nominal full-scale range equal to twice the applied VREF
voltage. Each input swings VREF VP-P, 180° out of phase from
one another for a total differential input of 2*VREF (refer to
Figure 23). Differential signaling offers several benefits over a
single-ended input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the SCLOCK pin to generate
a conversion result. The allowable frequency range for SCLOCK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLOCK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 12 for more
details.
ADC Transfer Function
The output coding for the ISL267440, ISL267450A is twos
complement. The first code transition occurs at successive LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the
ISL267450A is 2*VREF/4096, while the LSB size of the
ISL267440 is 2*VREF/1024. The ideal transfer characteristic
of the ISL267440, ISL267450A is shown in Figure 22.
VCM
VREF PP
VREF PP
VIN+
ISL267440,
ISL267450A
VIN–
FIGURE 23. DIFFERENTIAL INPUT SIGNALING
Figure 24 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
11
FN7708.0
December 5, 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL267450A.PDF ] | |
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