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PDF ISLA214P50 Data sheet ( Hoja de datos )
| Número de pieza | ISLA214P50 | |
| Descripción | 500MSPS ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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14-Bit, 500MSPS ADC
ISLA214P50
The ISLA214P50 is a 14-bit, 500MSPS analog-to-digital converter
designed with Intersil’s proprietary FemtoCharge™ technology on
a standard CMOS process. The ISLA214P50 is part of a
pin-compatible portfolio of 12 to 16-bit A/Ds with maximum
sample rates ranging from 130MSPS to 500MSPS.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single 500MHz
conversion clock is presented to the converter, and all interleave
clocking is managed internally. The proprietary Intersil Interleave
Engine (I2E) performs automatic correction of offset, gain, and
sample time mismatches between the unit ADCs to optimize
performance.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue offline and
continuous calibration commands as well as configure many
dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA214P50 is available in a 72 Ld QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 500MSPS
= 72.7dBFS fIN = 30MHz
= 70.6dBFS fIN = 363MHz
• SFDR @ 500MSPS
= 84dBc fIN = 30MHz
= 76dBc fIN = 363MHz
• Total Power Consumption = 835mW @ 500MSPS
Features
• Automatic Fine Interleave Correction Calibration
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
VINP
VINN
VCM
SHA
SHA
14-BIT
250 MSPS
ADC
VREF
Gain, Offset
and Skew
Adjustments
I2E
DIGITAL
ERROR
CORRECTION
D[13:0]P
D[13:0]N
ORP
ORN
14-BIT
250 MSPS
ADC
VREF
+
–
SPI
CONTROL
Pin-Compatible Family
MODEL
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
March 15, 2011
FN7571.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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ISLA214P50
Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)
PIN NUMBER
8, 9
10, 11
15
16
18
22, 23
24, 25
29
31
34
36
38
40
42
44
46
48
50
52
54
56
58
60
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D13
D12
D11
D10
D9
D8
D7
D6
RLVDS
CLKOUT
D5
D4
D3
D2
D1
D0
OR
SDO
CSB
SCLK
SDIO
AVSS
CMOS PIN FUNCTION
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
CMOS Bit 13 (MSB) Output
CMOS Bit 12 Output
CMOS Bit 11 Output
CMOS Bit 10 Output
CMOS Bit 9 Output
CMOS Bit 8 Output
CMOS Bit 7 Output
CMOS Bit 6 Output
LVDS Bias Resistor (connect to OVSS with 1%10kW)
CMOS Clock Output
CMOS Bit 5 Output
CMOS Bit 4 Output
CMOS Bit 3 Output
CMOS Bit 2 Output
CMOS Bit 1 Output
CMOS Bit 0 (LSB) Output
CMOS Over Range
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
5 FN7571.1
March 15, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
ISLA214P50
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
MIN MAX
SYMBOL CONDITIONS (Note 5) TYP (Note 5) UNITS
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
RIpd
RIpu
100 kΩ
100 kΩ
Differential Output Voltage (Note 10)
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
VT 3mA Mode
VOS 3mA Mode
tR
tF
1120
612
1150
240
240
1200
mVP-P
mV
ps
ps
Voltage Output High
VOH IOH = -500µA OVDD - 0.3 OVDD - 0.1
V
Voltage Output Low
VOL IOL = 1mA
0.1 0.3
V
Output Rise Time
tR 1.8 ns
Output Fall Time
tF 1.4 ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
I2E Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
Offset Mismatch-induced Spurious Power
I2E Settling Times
Minimum Duration of Valid Analog Input
Largest Interleave Spur
Total Interleave Spurious Power
Sample Time Mismatch Between Unit ADCs
Gain Mismatch Between Unit ADCs
Offset Mismatch Between Unit ADCs
SYMBOL
I2Epost_t
tTE
CONDITIONS
No I2E Calibration performed
Active Run state enabled
Calibration settling time for
Active Run state
Allow one I2E iteration of Offset,
Gain and Phase correction
fIN = 10MHz to 240MHz, Active
Run State enabled, in Track Mode
fIN = 10MHz to 240MHz, Active
Run State enabled and previously
settled, in Hold Mode
fIN = 260MHz to 490MHz, Active
Run State enabled, in Track Mode
fIN = 260MHz to 490MHz, Active
Run State enabled and previously
settled, in Hold Mode
Active Run State enabled, in
Track Mode,
signal in the
f1INst
is a broadband
Nyquist zone
Active Run State enabled, in
Track Mode,
signal in the
f2INndisNayqburoisatdzboanned
Active Run State enabled, in
Track Mode
MIN
(Note 5)
-75
TYP
-65
-70
-99
-80
-99
-75
-85
-75
25
0.01
1
MAX
(Note 5)
1000
100
UNITS
dBFS
dBFS
ms
µs
dBc
dBc
dBc
dBc
dBc
dBc
fs
%FS
mV
11 FN7571.1
March 15, 2011
Data
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