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PDF ISLA214S50 Data sheet ( Hoja de datos )
| Número de pieza | ISLA214S50 | |
| Descripción | 500/350 MSPS JESD204B High Speed Serial Output ADC | |
| Fabricantes | Intersil | |
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14-Bit, 500/350 MSPS JESD204B High Speed Serial
Output ADC
ISLA214S50
The ISLA214S50 is a series of low-power, high-performance,
14-bit, analog-to-digital converters. Designed with
FemtoCharge™ technology on a standard CMOS process, the
series supports sampling rates of up to 500MSPS. The
ISLA214S50 is part of a pin-compatible family of 12-, 14-, and
16-bit A/Ds with maximum sample rates ranging from
125MSPS to 500MSPS. The family minimizes power
consumption while providing state-of-the-art dynamic
performance.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Intersil Interleave Engine (I2E) performs automatic correction
of offset, gain, and sample time mismatches between the unit
ADCs to optimize performance.
The ISLA214S50 offers a highly configurable, JESD204B-
compliant, high speed serial output link. The link offers data
rates up to 4.375 Gbps per lane and multiple packing modes.
The link can be configured to use two or three lanes to
transmit the conversion data, allowing for flexibility in the
receiver design. The JESD204 transmitter also provides
deterministic latency and multi-chip time alignment support to
satisfy complex synchronization requirements.
A serial peripheral interface (SPI) port allows for extensive
configurability of the ADC and its JESD204B transmitter
including access to its built-in link and transport-layer test
patterns as well as the programmable clock divider, enabling
2x harmonic clocking.
The ISLA214S50 is available in a space-saving 7mmx7mm 48
Ld QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C)
Features
• JESD204A/B High Speed Data Interface
- JESD204A Compliant
- JESD204B Device Subclass 0 Compliant
- JESD204B Device Subclass 2 Compatible
- Up to 3 JESD204 Output Lanes Running up to 4.375Gbps
- Highly Configurable JESD204 Transmitter
• Multiple Chip Time Alignment and Deterministic Latency
Support (JESD204B Device Subclass 2)
• SPI Programmable Debugging Features and Test Patterns
• 48-pin QFN 7mmx7mm Package
Key Specifications
• SNR @ 500/350MSPS
73.1/74.1 dBFS fIN = 30MHz
71.0/71.6 dBFS fIN = 363MHz
• SFDR @ 500/350MSPS
87/87 dBc fIN = 30MHz
78/81 dBc fIN = 363MHz
• Total Power Consumption: 1060mW @ 500MSPS
Applications
• Radar and Satellite Antenna Array Processing
• Broadband Communications and Microwave Receivers
• High-Performance Data Acquisition
• Communications Test Equipment
• High-Speed Medical Imaging
Pin-Compatible Family
MODEL
ISLA214S50
ISLA214S35
RESOLUTION
14
14
SPEED
(MSPS)
500
350
PRODUCT
AVAILABILITY
Now
Soon
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
December 21, 2011
FN7973.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
ISLA214S50
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
23
0.75
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C.
ISLA214S50
ISLA214S35
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
(Note 6) TYP (Note 6) (Note 6) TYP (Note 6)
UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog Input
Range
VFS Differential
1.95 2.00 2.15
1.95 2.00 2.15
VP-P
Input Resistance
Input Capacitance
Full Scale Range Temp. Drift
Input Offset Voltage
Gain Error
Common-Mode Output
Voltage
RIN
CIN
AVTC
VOS
EG
VCM
Differential
Differential
Full Temp
600
13.3
100
-5.0 ±1 5.0
-2.6
0.94
600
13.3
100
-5.0 ±1 5.0
-2.6
0.94
Ω
pF
ppm/°C
mV
%
V
Common Mode Input Current
(per pin)
ICM
6.0 6.0 µA/MSPS
Clock Inputs
Inputs Common Mode
Voltage
0.9 0.9 V
CLKP, CLKN Swing
1.8 1.8 V
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7 1.8 1.9
1.7 1.8 1.9
V
1.8V Digital Supply Voltage
OVDD
1.7 1.8 1.9
1.7 1.8 1.9
V
1.8V Analog Supply Current
1.8V Digital Supply Current
IAVDD
IOVDD
I2E on, Fs/4 filter on,
Minimum number of lanes
active
359 385
222 248
313
159
mA
mA
5 FN7973.1
December 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
ISLA214S50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
90 -75
85
80
SFDR
75
70 SNR
65
-80
-85
-90
-95
-100
-105
HD3
HD2
60
200
250 300 350 400 450
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
500
550
-110
200
250 300 350 400 450
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs fSAMPLE
500
550
1200
1000
800
3 LANES
600
400
200
0
200 250 300 350 400 450 500 550
SAMPLE RATE (MSPS)
FIGURE 9. POWER vs fSAMPLE
4
3
2
1
0
-1
-2
-3
-4
0
5000
10000
15000
CODE
FIGURE 11. INTEGRAL NONLINEARITY
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
5000
10000
CODE
FIGURE 10. DIFFERENTIAL NONLINEARITY
15000
90
85
SFDR
80
75
SNR
70
65
60
700
800 900 1000 1100 1200 1300
VCM (mV)
FIGURE 12. SNR AND SFDR vs VCM
1400
1500
11
FN7973.1
December 21, 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet ISLA214S50.PDF ] | |
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