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PDF ISLA222P Data sheet ( Hoja de datos )
| Número de pieza | ISLA222P | |
| Descripción | 250MSPS/200MSPS/130MSPS ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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www.DataSheet.co.kr
Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA222P
The ISLA222P is a family of dual-channel 12-bit
analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA222P is part of a pin-compatible portfolio
of 12-bit and 14-bit dual-channel A/Ds with maximum sample
rates ranging from 130MSPS to 250MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA222P is available in a 72 lead QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 250/200/130MSPS
70.3/71.0/71.3dBFS fIN = 30MHz
68.5/68.8/68.4dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
85/87/86dBc fIN = 30MHz
73/75/80dBc fIN = 363MHz
• Total Power Consumption = 823mW @ 250MSPS
Features
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKP
CLKN
VINBP
VINBN
VCM
VINAN
VINAP
SHA
SHA
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
12-BIT
250 MSPS
ADC
VREF
12-BIT
250 MSPS
ADC
VREF
1.25V +–-
DIGITAL
ERROR
CORRECTION
SPI
CONTROL
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
Pin-Compatible Family
MODEL
ISLA224P25
ISLA224P20
ISLA224P13
ISLA222P25
ISLA222P20
ISLA222P13
RESOLUTION
14
14
14
12
12
12
SPEED
(MSPS)
250
200
130
250
200
130
June 17, 2011
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN7853.1
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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ISLA222P
Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)
PIN NUMBER
6, 7
12, 13
15
16
18
22, 23
24, 25
29
31
34
36
38
40
42
44
46
48
50
52
54
56
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VINBP, VINBN
VINAN, VINAP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11
D10
D9
D8
D7
D6
D5
D4
RLVDS
CLKOUT
D3
D2
D1
D0
OR
SDO
CSB
SCLK
SDIO
AVSS
CMOS PIN FUNCTION
Channel B Analog Input Positive, Negative
Channel A Analog Input Negative, Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
CMOS Bit 11 (MSB) Output
CMOS Bit 10 Output
CMOS Bit 9 Output
CMOS Bit 8 Output
CMOS Bit 7 Output
CMOS Bit 6 Output
CMOS Bit 5 Output
CMOS Bit 4 Output
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
CMOS Clock Output
CMOS Bit 3 Output
CMOS Bit 2 Output
CMOS Bit 1 Output
CMOS Bit 0 (LSB) Output
CMOS Over Range
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
5 FN7853.1
June 17, 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
ISLA222P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
MAX
TYP (Note 5) UNITS
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak-to-peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
VICM
VID
RIpd
RIpu
825 1575 mV
250 450 mV
100 kΩ
100 kΩ
Differential Output Voltage (Note 10)
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
VT 3mA Mode
VOS 3mA Mode
tR
tF
1120
612
1150
240
240
1200
mVP-P
mV
ps
ps
Voltage Output High
VOH IOH = -500µA
OVDD - 0.3 OVDD - 0.1
V
Voltage Output Low
VOL IOL = 1mA
0.1 0.3 V
Output Rise Time
tR 1.8 ns
Output Fall Time
tF 1.4 ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
CLKN
CLKP
tA
tCPD
CLKOUTN
CLKOUTP
D[11:0]N
D[11:0]P
LATENCY = L CYCLES
tDC
tPD
A DATA
N-L
B DATA A DATA
N-L N-L+1
B DATA
N-L+1
FIGURE 1. LVDS
B DATA A DATA B DATA
N-1 N
N
11
FN7853.1
June 17, 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet ISLA222P.PDF ] | |
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