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PDF W39V040B Data sheet ( Hoja de datos )
| Número de pieza | W39V040B | |
| Descripción | 512K X 8 CMOS FLASH MEMORY | |
| Fabricantes | Winbond | |
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W39V040B Data Sheet
Table of Contents-
512K × 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS............................................................................................................. 4
4. BLOCK DIAGRAM ...................................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 4
6. FUNCTIONAL DESCRIPTION.................................................................................................... 5
6.1 Interface Mode Selection and Description......................................................................... 5
6.2 Read (Write) Mode ............................................................................................................ 5
6.3 Reset Operation................................................................................................................. 5
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ........................... 5
6.5 Sector Erase Command .................................................................................................... 6
6.6 Program Operation ............................................................................................................ 6
6.7 Hardware Data Protection ................................................................................................. 6
6.8 WRITE OPERATION STATUS.......................................................................................... 6
7. REGISTER FOR LPC MODE ..................................................................................................... 9
7.1 General Purpose Inputs Register for LPC Mode............................................................... 9
7.2 Identification Input Pins ID[3:0] .......................................................................................... 9
7.3 Product Identification Registers......................................................................................... 9
8. TABLE OF OPERATING MODES ............................................................................................ 10
8.1 Operating Mode Selection - Programmer Mode.............................................................. 10
8.2 Operating Mode Selection - LPC Mode........................................................................... 10
8.3 LPC Cycle Definition........................................................................................................ 10
9. TABLE OF COMMAND DEFINITION ....................................................................................... 11
9.1 Embedded Programming Algorithm ................................................................................ 12
9.2 Embedded Erase Algorithm............................................................................................. 13
9.3 Embedded #Data Polling Algorithm................................................................................. 14
9.4 Embedded Toggle Bit Algorithm...................................................................................... 15
9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow ..... 16
10. ELECTRICAL CHARACTERISTICS......................................................................................... 17
10.1 Absolute Maximum Ratings......................................................................................... 17
10.2 Programmer interface Mode DC Operating Characteristics ....................................... 17
10.3 LPC Interface Mode DC Operating Characteristics .................................................... 18
10.4 Power-up Timing ......................................................................................................... 18
10.5 Capacitance................................................................................................................. 18
10.6 Programmer Interface Mode AC Characteristics ........................................................ 19
10.7 Read Cycle Timing Parameters .................................................................................. 20
Publication Release Date: December 12, 2005
- 1 - Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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W39V040B
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is
LPC interface mode. The Mode pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When ic
(Mode) pin is set to VDD, the device will be in the Programmer mode; while the Mode pin is set to low
state (or leaved no connection), it will be in the LPC mode. In Programmer mode, this device just
behaves like traditional flash parts with 8 data lines. But the row and column address inputs are
multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column
address are mapped to the lower internal address A[10:0]. For LPC mode, it complies with the LPC
Interface Specification, through the LAD[3:0] to communicate with the system chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040B is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As for in the LPC interface mode, the read or write is determined
by the "START CYCLE ". Refer to the LPC cycle definition and timing waveforms for further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on
programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If
#WP pin is tied to low state before power on, the other sectors will not be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). You can check the
DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is
“0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be
programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it
means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.
Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in
high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if
the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Publication Release Date: December 12, 2005
- 5 - Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
W39V040B
9. TABLE OF COMMAND DEFINITION
COMMAND
DESCRIPTION
Read
Sector Erase
Byte Program
Product ID Entry
Product ID Exit (4)
Product ID Exit (4)
NO. OF
Cycles (1)
1
6
4
3
3
1
1ST CYCLE
Addr. Data
AIN DOUT
5555 AA
5555 AA
5555 AA
5555 AA
XXXX F0
2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555 80 5555
5555 A0 AIN
5555 90
5555 F0
AA 2AAA
DIN
55
SA(5) 30
Notes:
1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]
3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 7XXXXh for Unique Sector7 (Boot Sector)
SA = 6XXXXh for Unique Sector6
SA = 5XXXXh for Unique Sector5
SA = 4XXXXh for Unique Sector4
SA = 3XXXXh for Unique Sector3
SA = 2XXXXh for Unique Sector2
SA = 1XXXXh for Unique Sector1
SA = 0XXXXh for Unique Sector0
- 11 -
Publication Release Date: December 12, 2005
Revision A4
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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