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W9864G2IB 데이터시트 PDF




Winbond에서 제조한 전자 부품 W9864G2IB은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 W9864G2IB 기능
기능 512K X 4 BANKS X 32BITS SDRAM
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W9864G2IB 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
W9864G2IB
512K × 4 BANKS × 32BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 3
2. FEATURES...................................................................................................................................... 3
3. AVAILABLE PART NUMBER .......................................................................................................... 3
4. BALL CONFIGURATION................................................................................................................. 4
5. BALL DESCRIPTION ...................................................................................................................... 5
6. BLOCK DIAGRAM........................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1 Power Up and Initialization ................................................................................................. 7
7.2 Programming Mode Register .............................................................................................. 7
7.3 Bank Activate Command .................................................................................................... 7
7.4 Read and Write Access Modes .......................................................................................... 7
7.5 Burst Read Command ........................................................................................................ 8
7.6 Burst Command .................................................................................................................. 8
7.7 Read Interrupted by a Read ............................................................................................... 8
7.8 Read Interrupted by a Write................................................................................................ 8
7.9 Write Interrupted by a Write ................................................................................................ 8
7.10 Write Interrupted by a Read................................................................................................ 8
7.11 Burst Stop Command.......................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode......................................................................... 9
7.13 Addressing Sequence of Interleave Mode.......................................................................... 9
7.14 Auto-precharge Command................................................................................................ 10
7.15 Precharge Command........................................................................................................ 10
7.16 Self Refresh Command..................................................................................................... 10
7.17 Power Down Mode............................................................................................................ 11
7.18 No Operation Command ................................................................................................... 11
7.19 Deselect Command .......................................................................................................... 11
7.20 Clock Suspend Mode........................................................................................................ 11
8. OPERATION MODE...................................................................................................................... 12
9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13
9.1 Absolute Maximum Ratings .............................................................................................. 13
9.2 Recommended DC Operating Conditions ........................................................................ 13
Publication Release Date: Sep. 17, 2009
- 1 - Revision A01
Datasheet pdf - http://www.DataSheet4U.net/




W9864G2IB pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
W9864G2IB
4. BALL CONFIGURATION
Top View
123456789
A
DQ26
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1
L
VDDQ
M
VSSQ
N
VSSQ
P
DQ11
R
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BS1 NC
BS0 CS RAS
CAS WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
-4-
Publication Release Date: Sep. 17, 2009
Revision A01
Datasheet pdf - http://www.DataSheet4U.net/

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W9864G2IB 전자부품, 판매, 대치품
www.DataSheet.co.kr
W9864G2IB
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD + 0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the
DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max.).
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
Publication Release Date: Sep. 17, 2009
- 7 - Revision A01
Datasheet pdf - http://www.DataSheet4U.net/

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부품번호상세설명 및 기능제조사
W9864G2IB

512K X 4 BANKS X 32BITS SDRAM

Winbond
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W9864G2IH

512K X 4 BANKS X 32BITS SDRAM

Winbond
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