PDF 74HC74AN Data sheet ( Hoja de datos )

Número de pieza	74HC74AN
Descripción	Dual D Flip-Flop
Fabricantes	ON Semiconductor
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No Preview Available ! www.DataSheet.co.kr MC74HC74A Dual D Flip-Flop with Set and Reset High–Performance Silicon–Gate CMOS The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information at a D–input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip–flop. The Set and Reset inputs are asynchronous. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 128 FETs or 32 Equivalent Gates LOGIC DIAGRAM RESET 1 1 DATA 1 CLOCK 1 2 3 5 Q1 6 Q1 SET 1 4 13 RESET 2 PIN 14 = VCC PIN 7 = GND DATA 2 CLOCK 2 12 11 9 Q2 8 Q2 10 SET 2 FUNCTION TABLE Inputs Set Reset Clock Data LH HL LL HH HH HH HH HH XX XX XX H L LX HX X Outputs QQ HL LH H* H* HL LH No Change No Change No Change Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. http://onsemi.com PDIP–14 N SUFFIX CASE 646 SOIC–14 D SUFFIX CASE 751A MARKING DIAGRAMS 14 MC74HC74AN AWLYYWW 1 14 HC74A AWLYWW 1 14 TSSOP–14 DT SUFFIX CASE 948G HC 74A ALYW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week PIN ASSIGNMENT RESET 1 DATA 1 CLOCK 1 SET 1 Q1 Q1 GND 1 2 3 4 5 6 7 14 VCC 13 RESET 2 12 DATA 2 11 CLOCK 2 10 SET 2 9 Q2 8 Q2 ORDERING INFORMATION Device Package Shipping MC74HC74AN PDIP–14 2000 / Box MC74HC74AD SOIC–14 55 / Rail MC74HC74ADR2 SOIC–14 2500 / Reel MC74HC74ADT TSSOP–14 96 / Rail MC74HC74ADTR2 TSSOP–14 2500 / Reel © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 8 1 Publication Order Number: MC74HC74A/D Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr MC74HC74A CLOCK Q or Q tf 90% 50% 10% tw 1/fmax 90% 50% 10% tPLH tTLH tr tPHL tTHL Figure 1. SWITCHING WAVEFORMS tw VCC SET OR 50% RESET GND tPHL Q OR Q 50% Q OR Q tPLH 50% CLOCK trec 50% Figure 2. VCC GND VCC GND DATA CLOCK VALID 50% tsu th 50% Figure 3. 4, 10 SET 2, 12 DATA 1, 13 RESET TEST POINT VCC OUTPUT GND DEVICE UNDER VCC TEST CL GND *Includes all probe and jig capacitance Figure 4. EXPANDED LOGIC DIAGRAM 3, 11 CLOCK 5, 9 Q 6, 8 Q http://onsemi.com 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page

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