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PDF NVT2001 Data sheet ( Hoja de datos )
| Número de pieza | NVT2001 | |
| Descripción | (NVT2001 / NVT2002) Bidirectional voltage level translator | |
| Fabricantes | NXP Semiconductors | |
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NVT2001; NVT2002
Bidirectional voltage level translator for open-drain and
push-pull applications
Rev. 2 — 26 October 2011
Product data sheet
1. General description
The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V
(Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage translations between
1.0 V and 5 V without the need for a direction pin in open-drain or push-pull applications.
Bit widths ranging from 1-bit or 2-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
2.5 V Vref(A) and 5 V Vref(B)
3.3 V Vref(A) and 5 V Vref(B)
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
7. Application design-in information
The NVT2001/02 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2001/02 is
ideal for use in applications where an open-drain driver is connected to the data I/Os. The
NVT2001/02 can also be used in applications where a push-pull driver is connected to the
data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
Vpu(D) = 3.3 V(1)
200 kΩ
Vref(A) = 1.8 V(1)
VREFA
2
NVT2002
8 EN
7 VREFB
RPU RPU
VCC
RPU RPU
SCL A1 3 SW 6 B1
I2C-BUS
MASTER
SDA
A2 4 SW 5 B2
VCC
SCL
I2C-BUS
DEVICE
SDA
GND
1
GND
GND
002aae134
(1) The applied voltages at Vref(A) and Vpu(D) should be such that Vref(B) is at least 1 V higher than
Vref(A) for best translator operation.
Fig 6. Typical application circuit (switch always enabled)
Table 4. Application operating conditions
Refer to Figure 6.
Symbol Parameter
Conditions
Vref(B)
VI(EN)
Vref(A)
Isw(pass)
Iref
Tamb
reference voltage (B)
input voltage on pin EN
reference voltage (A)
pass switch current
reference current
ambient temperature
transistor
operating in
free-air
[1] All typical values are at Tamb = 25 C.
Min Typ[1]
Vref(A) + 0.6
Vref(A) + 0.6
0
2.1
2.1
1.5
- 14
-5
40 -
Max
5
5
4.4
-
-
+85
Unit
V
V
V
mA
A
C
NVT2001_NVT2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 October 2011
© NXP B.V. 2011. All rights reserved.
5 of 23
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
11. Dynamic characteristics
11.1 Open-drain drivers
Table 9. Dynamic characteristics for open-drain drivers
Tamb = 40 C to +85 C; VI(EN) = Vref(B); Rbias(ext) = 200 k; CVREFB = 0.1 F; unless otherwise
specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Refer to Figure 12
tPLH LOW to HIGH
propagation delay
from (input) Bn [1] Ron (CL + Cio(on)) ns
to (output) An
tPHL HIGH to LOW
propagation delay
from (input) Bn
to (output) An
Ron (CL + Cio(on)) ns
[1] See graphs based on Ron typical and Cio(on) + CL = 50 pF.
5.5 V
1.5 V swing
0.1 μF
SIGNAL
GENERATOR
200 kΩ
EN VREFB
DUT
VREFA
6.6 V
500 Ω
50 pF
450 Ω
1.5 V
1 V/div
Bn
GND
An
GND
002aaf348
002aaf347
40 ns/div
Fig 10. AC test setup
Fig 11. Example of typical AC waveform
from output under test
VTT
RL
S1
S2 (open)
CL
002aab845
input
VM
output
VM
VIH
VM
VIL
VOH
VM
VOL
002aab846
a. Load circuit
b. Timing diagram; high-impedance scope probe
used
S2 = translating down, and same voltage.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr 2 ns; tf 2 ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 12. Load circuit for outputs
NVT2001_NVT2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 October 2011
© NXP B.V. 2011. All rights reserved.
11 of 23
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet NVT2001.PDF ] | |
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