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PDF PSMN8R0-30YL Data sheet ( Hoja de datos )
| Número de pieza | PSMN8R0-30YL | |
| Descripción | N-channel MOSFET | |
| Fabricantes | NXP Semiconductors | |
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PSMN8R0-30YL
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
Rev. 2 — 16 May 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference data
Symbol
VDS
Parameter
drain-source
voltage
Conditions
Tj ≥ 25 °C; Tj ≤ 175 °C
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Static characteristics
RDSon
drain-source
VGS = 10 V; ID = 15 A; Tj = 25 °C
on-state resistance
Dynamic characteristics
QGD
gate-drain charge VGS = 10 V; ID = 45 A; VDS = 15 V;
see Figure 14; see Figure 15
QG(tot)
total gate charge
VGS = 4.5 V; ID = 45 A; VDS = 15 V;
see Figure 14; see Figure 15
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C;
ID = 62 A; Vsup ≤ 30 V; RGS = 50 Ω;
unclamped
Min Typ Max Unit
- - 30 V
- - 62 A
- - 56 W
- 6.9 8.3 mΩ
- 4 - nC
- 9 - nC
- - 21 mJ
Datasheet
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1 page  
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NXP Semiconductors
PSMN8R0-30YL
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
6. Characteristics
Table 6. Characteristics
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 12
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 13
RG gate resistance
Dynamic characteristics
VGS = 10 V; ID = 15 A; Tj = 25 °C
f = 1 MHz
QG(tot)
total gate charge
ID = 45 A; VDS = 15 V; VGS = 4.5 V;
see Figure 14; see Figure 15
ID = 45 A; VDS = 15 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS
QGS(th)
gate-source charge
pre-threshold gate-source
charge
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 45 A; VDS = 15 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th-pl)
post-threshold gate-source
charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau voltage
VDS = 15 V; see Figure 14;
see Figure 15
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 17
VDS = 15 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
VDS = 15 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
PSMN8R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2011
Min Typ Max Unit
30 - - V
27 - - V
1.3 1.7 2.15 V
0.5 - - V
- - 2.55 V
-
0.02 1
µA
- - 100 µA
- 10 100 nA
- 10 100 nA
- 10.4 12.2 mΩ
- - 15 mΩ
- 6.9 8.3 mΩ
- 2.03 - Ω
- 9 - nC
- 18.3 - nC
- 16.1 - nC
- 2.7 - nC
- 1.5 - nC
- 1.2 - nC
- 4 - nC
- 3.2 - V
- 1005 - pF
- 200 - pF
- 102 - pF
- 15 - ns
- 29 - ns
- 21 - ns
- 8 - ns
© NXP B.V. 2011. All rights reserved.
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Datasheet
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www.DataSheet.co.kr
NXP Semiconductors
PSMN8R0-30YL
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
PSMN8R0-30YL v.2
Modifications:
20110516
Product data sheet
• Various changes to content.
PSMN8R0-30YL v.1 20110217
Product data sheet
Change notice
-
-
Supersedes
PSMN8R0-30YL v.1
-
PSMN8R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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