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부품번호 UM10430
기능 LPC18xx ARM Cortex-M3 microcontroller
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UM10430 데이터시트, 핀배열, 회로
UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 2.8 — 10 December 2015
User manual
Document information
Info Content
Keywords
LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x,
LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20,
LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3,
SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
Abstract
LPC18xx user manual




UM10430 pdf, 반도체, 판매, 대치품
NXP Semiconductors
UM10430
Chapter :
Revision history …continued
Rev
Date
Description
Modifications:
Updated Table 48 “IAP Copy RAM to Flash command”.
Added a bullet to Section 5.2 “Basic configuration”. If the application uses the IAP interface, it must
reserve the SRAM space used by IAP as outlined in Section 5.4.5.8 “RAM used by IAP command
handler”.
Updated Section 5.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from
0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.
Updated Section 5.4.5.7 “RAM used by ISP”; removed command handler from the title and updated
text.
Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.
Updated Figure 32 “AES endianness”.
2.6
20150210
LPC18xx user manual
UM10430
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 2.8 — 10 December 2015
© NXP B.V. 2015. All rights reserved.
4 of 1284

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UM10430 전자부품, 판매, 대치품
NXP Semiconductors
UM10430
Chapter :
Revision history …continued
Rev
Date
Description
Modifications:
Description of the SDIS bit updated in for USB0 stream mode in Table 410/Table 411 and for USB1
stream mode in Table 471/Table 472.
Updated description of access types to the USB descriptors. See Table 421 “Endpoint capabilities
and characteristics” and Table 425 “dTD token”.
Use of EMC_CLK pins clarified for SDRAM devices. See Section 21.2.
Pin description of pins SD_VOLT[2:0] updated in Table 274.
Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router
registers. See Table 72, Table 75 to Table 83, and Section 13.5.1 “Determine the cause of a core
reset”.
Table 183 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.
USB driver code listing corrected. See Section 24.5 “USB API”.
Register RESET_EXT_STAT4 removed. See Table 152.
SDRAM address mappings added in Table 364.
Device MX25L6435EM2I-10G added to Table 18 “QSPI devices supported by the boot code and the
SPIFI API”.
Table 4 “Ordering options (parts with on-chip flash)” corrected. ULPI not available on 144-pin and
100-pin packages.
Editorial updates to Section 4.3.5 “Boot image creation” and Figure 13 “Image encryption flow”
added.
Editorial edits to Chapter 6 “LPC18xx Security API”. Section “CMAC using AES hardware
acceleration” removed.
Section 11.2.1 “Configuring the BASE_M3_CLK for high operating frequencies” corrected to ensure
safe operation of the clock ramping procedure.
Figures and tables in Section 40.7.2 “I2S operating modes” corrected.
Table 39 “LPC18xx part identification numbers” description of word1 corrected.
Part LPC1850FBD208 removed.
OTP memory size available for general-purpose use corrected. See Section 1.2 and Table 7.
Details about encryption of the image header added in Section 4.3.4 “Boot image header format”.
Figure 11 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.
Bit description of Table 300 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit
description” updated. Host clock is the SD_CLK clock.
Security features updates. FIPS compliancy added. See Section 6.2.
Section 28.4.3 “SCT Example” updated.
Figure 103 “Repetitive Interrupt Timer (RIT) block diagram” corrected.
ISP mode added to Figure 11 “Boot process for parts without flash”.
Chapter “LPC18xx API General error codes” added.
2.2
Modifications:
20130125
LPC18xx user manual.
GPIO group interrupt wake-up from power-down modes corrected in Section 16.3.2. Only wake-up
from sleep mode supported.
Section 4.3.5.4.1 “Supported QSPI devices” moved to Chapter 4 “LPC18xx Boot ROM”.
SPIFI register map and register descriptions added in Chapter 19 “LPC18xx SPI Flash Interface
(SPIFI)”.
Bit description of Table 924 “CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A
4008 (C_CAN1)) bit description” corrected.
Bit clock calculation and bit description corrected in Section 41.6.1.4 “CAN bit timing register”.
UM10430
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 2.8 — 10 December 2015
© NXP B.V. 2015. All rights reserved.
7 of 1284

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