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부품번호 ATXMEGA192D3
기능 8/16-bit XMEGA D3 Microcontroller
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ATXMEGA192D3 데이터시트, 핀배열, 회로
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Features
High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
Non-volatile Program and Data Memories
– 64K - 256K Bytes of In-System Self-Programmable Flash
– 4K - 8K Bytes Boot Code Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 16K Bytes Internal SRAM
Peripheral Features
– Four-channel Event System
– Five 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
One Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on two Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Three USARTs
IrDA Extension on 1 USART
– Two Two-Wire Interfaces with dual address match(I2C and SMBus compatible)
– Two SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– One Sixteen-channel, 12-bit, 200ksps Analog to Digital Converter
– Two Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interface
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
Industrial control
Factory automation
Climate control
ZigBee
Building control
Motor control
Board control
Networking
White Goods
Optical
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8/16-bit
XMEGA D3
Microcontroller
ATxmega256D3
ATxmega192D3
ATxmega128D3
ATxmega64D3
8134I–AVR–12/10
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XMEGA D3
3. Overview
The Atmel® AVR® XMEGA D3 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR® enhanced RISC architecture. By execug
powerful instructions in a single clock cycle, the XMEGA D3 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA D3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel Event System, Pro-
grammable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time
Counter (RTC), five flexible 16-bit Timer/Counters with compare modes and PWM, three
USARTs, two Two-Wire Interface (TWIs), two Serial Peripheral Interfaces (SPIs), one 16-chan-
nel 12-bit ADC with optional differential input with programmable gain, two analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available.
The XMEGA D3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Event System, Interrupt Controller and all peripherals
to continue functioning. The Power-down mode saves the SRAM and register contents but stops
the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset.
In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the appli-
cation to maintain a timer base while the rest of the device is sleeping. In Standby mode, the
Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows
very fast start-up from external crystal combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further
reduce power consumption, the peripheral clock for each individual peripheral can optionally be
stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in
the device can use any interface to download the application program to the Flash memory. The
Bootloader software in the Boot Flash section will continue to run while the Application Flash
section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC
CPU with In-System Self-Programmable Flash, the Atmel XMEGA D3 is a powerful microcon-
troller family that provides a highly flexible and cost effective solution for many embedded
applications.
The XMEGA D3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
8134I–AVR–12/10
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XMEGA D3
6. AVR CPU
6.1 Features
6.2 Overview
8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
The Atmel® AVR® XMEGATM D3 uses the 8/16-bit AVR CPU. The main function of the AVR CPU
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations and control peripherals. Interrupt handling is described in a separate sec-
tion. Figure 6-1 on page 7 shows the CPU block diagram.
Figure 6-1. CPU block diagram
DATA BUS
Program
Counter
OCD
Flash
Program
Memory
Instruction
Register
32 x 8 General
Purpose
Registers
STATUS/
CONTROL
Instruction
Decode
ALU
Multiplier/
DES
Peripheral
Module 1
Peripheral
Module 2
DATA BUS
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
8134I–AVR–12/10
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ATXMEGA192D3

8/16-bit XMEGA D3 Microcontroller

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ATxmega192D3

8/16-bit Atmel AVR XMEGA D3 Microcontroller

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