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W681310 데이터시트 PDF




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부품번호 W681310 기능
기능 3V SINGLE CHANNEL VOICEBAND CODEC
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W681310 데이터시트, 핀배열, 회로
W681310
W681310
3V SINGLE CHANNEL
VOICEBAND CODEC
Data Sheet
Revision B18
-1-




W681310 pdf, 반도체, 판매, 대치품
W681310
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF cONTENTS ....................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 9
7.1. Transmit Path ................................................................................................................................ 9
7.2. Receive Path ............................................................................................................................... 10
7.3. Power Management..................................................................................................................... 11
7.3.1. Analog and Digital Supply ..................................................................................................... 11
7.3.2. Analog Ground Reference Bypass ....................................................................................... 11
7.3.3. Analog Ground Reference Voltage Outpt ............................................................................. 11
7.4. PCM Interface .............................................................................................................................. 11
7.4.1. Long Frame Sync.................................................................................................................. 11
7.4.2. Short Frame Sync ................................................................................................................. 12
7.4.3. General Circuit Interface (GCI) ............................................................................................. 12
7.4.4. Interchip Digital Link (IDL)..................................................................................................... 12
7.4.5. System Timing ...................................................................................................................... 13
8. TIMING DIAGRAMS.......................................................................................................................... 14
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21
9.1. Absolute Maximum Ratings ......................................................................................................... 21
9.2. Operating Conditions ................................................................................................................... 21
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22
10.1. General Parameters .................................................................................................................. 22
10.2. Analog Signal Level and Gain Parameters ............................................................................... 23
10.3. Analog Distortion and Noise Parameters .................................................................................. 24
10.4. Analog Input and Output Amplifier Parameters......................................................................... 25
10.5. Digital I/O ................................................................................................................................... 27
10.5.1. -Law Encode Decode Characteristics............................................................................... 27
10.5.2. A-Law Encode Decode Characteristics .............................................................................. 28
Publication Release Date: February 2015
- 4 - Revision B18

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W681310 전자부품, 판매, 대치품
W681310
6. PIN DESCRIPTION
Pin Pin
Name No.
Functionality
VREF
1
This pin is used to bypass the on-chip VDD/2 voltage reference. It needs to be decoupled to VSS
through a 0.1 F ceramic decoupling capacitor. No external loads should be tied to this pin.
RO-
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kload to 0.886
volt peak referenced to the analog ground level.
PAI 3 This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
PAO+
4
Inverting power amplifier output. The PAO- and PAO+ can drive a 300 load differentially to
1.772 volt peak referenced to the VAG voltage level.
5
Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 load differentially
to 1.772 volt peak referenced to the VAG voltage level.
VDD
FSR
PCMR
6 Power supply. This pin should be decoupled to VSS with a 0.1F ceramic capacitor.
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
7 channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
8 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
PUI
MCLK
BCLKT
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
9 selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
11
kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended
to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in
the case of 256 and 512 kHz frequency.
12
PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI
mode and 256 kHz to 4800kHz in all other PCM modes.
PCMT 13 PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST 14 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
Publication Release Date: February 2015
- 7 - Revision B18

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부품번호상세설명 및 기능제조사
W681310

3V SINGLE-CHANNEL VOICEBAND CODEC

Winbond
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W681310

3V SINGLE CHANNEL VOICEBAND CODEC

Nuvoton Technology
Nuvoton Technology

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