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PDF BR25S128-W Data sheet ( Hoja de datos )
| Número de pieza | BR25S128-W | |
| Descripción | SPI BUS | |
| Fabricantes | ROHM Semiconductor | |
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High Reliability Series Serial EEPROMs
SPI BUS
BR25□□□□family
BR25S□□□ Series
No.10001EBT08
□□□●Description
BR25S
series is a serial EEPROM of SPI BUS interface method.
●Features
1) High speed clock action up to 20MHz (Max.)
2) Wait function by HOLDB terminal
3) Part or whole of memory arrays settable as read only memory area by program
4) 1.7～5.5V single power source action most suitable for battery use
5) Page write mode useful for initial value write at factory shipment
6) Highly reliable connection by Au pad and Au wire
7) For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)
8) Auto erase and auto end function at data rewrite
9) Low current consumption
At write action (5V)
: 1.5mA (Typ.)
At read action (5V)
: 1.0mA (Typ.)
At standby action (5V) : 0.1μA (Typ.)
10) Address auto increment function at read action
11) Write mistake prevention function
Write prohibition at power on
Write prohibition by command code (WRDI)
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Write prohibition by WPB pin
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage
12) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 Package
13) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
14) Data kept for 40 years
15) Data rewrite up to 1,000,000 times
●Page Write
Page
Part Number
32Byte
BR25S320-W
BR25S640-W
64Byte
BR25S128-W
BR25S256-W
●BR25S□□□ series
Capacity
Bit format
Power source
voltage
32Kbit 4K×8 1.7V～5.5V
64Kbit 8K×8 1.7V～5.5V
128Kbit 16K×8 1.7V～5.5V
256Kbit 32K×8 1.7V～5.5V
SOP8
●
●
●
●
SOP-J8
●
●
●
●
SSOP-B8 TSSOP-B8 MSOP8 TSSOP-B8J
● ●● ●
● ●● ●
●●
VSON008
X2030
●
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.12 - Rev.B
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
BR25S□□□ Series
●Characteristic data (The following characteristic data are Typ. Values.)
Technical Note
2.6 1.5 1.5
2.5
2.4
SPEC
Ta=-40℃
2.3 Ta=25℃
Ta=85℃
SPEC
1
Ta=-40℃
0.5 Ta=25℃
Ta=85℃
0
1 SPEC
Ta=-40℃
0.5 Ta=25℃
Ta=85℃
0
2.2
0
0.4 0.8
IOH[mA]
1.2
Fig.9 "H" output voltage VOH1 (Vcc=2.5V)
4
DATA=00h
3 Ta=-40℃
Ta=25℃
Ta=85℃
2
SPEC
1
-0.5
0123456
Vcc[V]
-0.5
0
Fig.10 Input leak current ILI(CSB,SCK,SI,HOLDB,WPB)
123456
VOUT[V]
Fig.11 Output leak current ILO(SO)
4
DATA=00h
3
Ta=-40℃
Ta=25℃
2 Ta=85℃
SPEC
10
DATA=00h
8
Ta=-40℃
6 Ta=25℃
Ta=85℃
4
SPEC
1
2
0
0123456
Vcc[V]
Fig.12 Current consumption at WRITE operation ICC3
(BR25S320/640-W)
0
0123456
Vcc[V]
Fig.13 Current Consumption at WRITE operation ICC3
(BR25S128/256-W)
5
4
Ta=-40℃
3 Ta=25℃
Ta=85℃
2
1
SPEC
1000
Ta=-40℃
Ta=25℃
Ta=85℃
100
10 SPEC
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SPEC
SPEC
0
-1
0123456
Vcc[V]
Fig.15 Current Consumption at standby operation ISB
1
0
SPEC
12345
Vcc[V]
Fig.16 SCK frequency fSCK
6
0
0123456
Vcc[V]
Fig.14 Current Consumption at READ operation ICC10
140
120
100
80
60
40
20
0
0
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
12345
Vcc[V]
Fig.17 SCK high time tSCKWH
6
140
120
100
80
60
40
20
0
0
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
12345
Vcc[V]
Fig.18 SCK low time tSCKWL
6
300
250
200
150
100
50
0
0
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
12345
Vcc[V]
Fig.19 CSB high time tCS
6
120
100
80
60
40
20
0
0
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
12345
Vcc[V]
Fig.20 CSB setup time tCSS
6
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
5/18
2010.12 - Rev.B
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
BR25S□□□ Series
Technical Note
●Method to cancel each command
○READ, RDSR
・Method to cancel : cancel by CSB = “H”.
Ope code
8 bits
Address
16 bits
Data
8 bits
Cancel available in all areas of read mode
Fig.40 READ cancel valid timing
Ope code
Data
8 bits
8 bits
Cancel available in all
areas of rdsr mode
Fig.41 RDSR cancel valid timing
○WRITE、PAGE WRITE
a：Ope code or address input area
Cancellation is available by CSB=”H”.
b：Data input area (D7～D1 input area)
Cancellation is available by CSB=”H”.
c：Data input area (D0 area)
In this area, cancellation is not available.
When CSB is set HIGH, write starts.
d：tE/W area
In the area c, by rising CSB, write starts.
While writing, by any input, cancellation cannot be made.
Ope code
8bits
Address
16bits
a
Data
8bits
b
tE/W
d
c
SCK
SI D7 D6 D5 D4 D3 D2 D1 D0
bc
Fig.42 WRITE cancel valid timing
Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again.
Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is
recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more.
○WRSR
a：From ope code to 15-th clock rise
Cancellation is available by CSB=”H”.
b：From 15-th clock rise to 16-th clock rise (write enable area)
In this area, cancellation is not available.
When CSB is set HIGH, write starts.
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c：After 16-th clock rise.
Cancellation is available by CSB=”H”.
However, if write starts (CSB is rised)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
SCK
14 15 16 17
SI D1 D0
ab
c
Ope code
Data
tE/W
8 bits
8 bits
a
c
b
Fig.43 WRSR cancel valid timing
Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again
Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it
is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more.
○WREN/WRDI
a：From ope code to 7-th clock rise, cancellation is available by CSB = “H”.
b：Cancellation is not available 7-th clock.
SCK
678
Ope code
8 bits
a
b
Fig.44 WREN/WRDI cancel valid timing
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
11/18
2010.12 - Rev.B
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet BR25S128-W.PDF ] | |
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