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BU9890GUL-W PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BU9890GUL-W
기능 Silicon Monolithic Integrated Circuit
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BU9890GUL-W 데이터시트, 핀배열, 회로
STRUCTURE
PRODUCT
PART NUMBER
PHYSICAL DIMENSION
BLOCK DIAGRAM
USE
FEATURES
Silicon Monolithic Integrated Circuit
4K×8 bit Electrically Erasable PROM
BU9890GUL-W
Fig.-1(VCSP50L1)
Fig.-2
General purpose
・4K words × 8 bits architecture serial EEPROM
・Wide operating voltage range (1.7V~3.6V)
・Two wire serial interface
・Self-timed write cycle with automatic erase
・32 byte Page Write mode
・Low power consumption。
Write (3.3V) : 0.6mA (Typ.)
Read (3.6V) : 0.6mA (Typ.)
Standby (3.6V) : 0.1μA (Typ.)
・DATA security
Write protect feature (WP pin)
Inhibit to WRITE at low VCC
・WLCSP 6pin package
・High reliability fine pattern CMOS technology
・Endurance : 100,000 erase/write cycles
・Data retention : 40 years
・Filtered inputs in SCL・SDA for noise suppression
・Initial data FFh in all address
・Pull-up resistor inputs in SCL・SDA
ABSOLUTE MAXIMUM RATING (Ta=25℃
Parameter
Supply Voltage
Symbol
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VCC
Rating
-0.3~6.5
Unit
V
Power Dissipation
Pd
220 *1
mW
Storage Temperature
Tstg
-65~125
Operating Temperature Topr
-40~85
Terminal Voltage
-0.3~Vcc+1.0 *2
V
*1 Degradation is done at 2.2mW/℃(*1) for operation above 25℃
*2 Maximum value of Terminal Voltage is below 6.5V.
1/13
◇RECOMMENDED OPERATING CONDITION
Parameter
Supply Voltage
Write
Read
Input Voltage
Symbol
Vcc
VIN
Rating
2.7~3.3
1.7~3.6
0~Vcc
REV. A
Unit
V
V
Datasheet pdf - http://www.DataSheet4U.net/




BU9890GUL-W pdf, 반도체, 판매, 대치품
◇BLOCK DIAGRAM
32 kbit EEPROM ARRAY
12bit
ADDRESS
DECODER
SLAVE・WORD
12bit ADDRESS REGISTER
8bit
DATA
REGISTER
Vcc
GND
WP
TEST
START
STOP
CONTOROL LOGIC
HIGH VOLTAGE GEN.
VCC LEVEL
ACK
SCL
SDA
Fig.-2 BLOCK DIAGRAM
TEST Pin Connect with GND
4/13
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REV. A
Datasheet pdf - http://www.DataSheet4U.net/

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BU9890GUL-W 전자부품, 판매, 대치품
◇SYNCHRONOUS DATA TIMING
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tR tF tHIGH
tSU:DAT
tLOW
tPD
tHD:DAT
tDH
7/13
SCL
SDA
tSU:STA
tHD:STA
tSU:STO
START BIT
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Fig.-4 SYNCHRONOUS DATA TIMING
STOP BIT
○SDA data is latched into the chip at the rising edge of SCL clock.
○Output date toggles at the falling edge of SCL clock.
◇WRITE CYCLE TIMING
SCL
SDA
D0
WRITE DATA(n)
ACK
tWR
STOP CONDITION
START CONDITION
Fig.-5 WRITE CYCLE TIMING
REV. A
Datasheet pdf - http://www.DataSheet4U.net/

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전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


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부품번호상세설명 및 기능제조사
BU9890GUL-W

Silicon Monolithic Integrated Circuit

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