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PDF AD7986 Data sheet ( Hoja de datos )
| Número de pieza | AD7986 | |
| Descripción | ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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18-Bit, 2 MSPS PulSAR
15 mW ADC in LFCSP (QFN)
AD7986
FEATURES
18-bit resolution with no missing codes
Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low)
Low power dissipation
15 mW at 2 MSPS, with external reference
26 mW at 2 MSPS with internal reference
INL: ±1 LSB typical, ±2.5 LSB maximum
SNR
95.5 dB, with on-chip reference
97.0 dB, with external reference
4.096 V internal reference: typical drift of 10 ppm/°C
True differential analog input voltage range: ±VREF
0 V to VREF with VREF up to 5.0 V
Allows use of any input range
No pipeline delay
Logic interface: 1.8 V/2.5 V/2.7 V
Serial interface: SPI/QSPI™/MICROWIRE™/DSP compatible
Ability to daisy-chain multiple ADCs with busy indicator
20-lead 4 mm × 4 mm LFCSP (QFN)
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems
APPLICATION DIAGRAM
1.8V
V+ TO
5V 2.5V 2.7V
0V
TO
VREF
VREF
TO
0V
15Ω
2.7nF
V–
V+
15Ω
2.7nF
V–
BVDD AVDD, VIO
IN+ DVDD TURBO
AD7986
SDI
SCK
IN– SDO
REF GND1 CNV
10µF
NOTES
1. GND REFERS TO REFGND, AGND, AND DGND.
Figure 1.
VIO
3- OR 4-WIRE
INTERFACE:
SPI, CS
DAISY CHAIN
(TURBO = LOW)
GENERAL DESCRIPTION
The AD7986 is an 18-bit, 2 MSPS successive approximation,
analog-to-digital converter (ADC). It contains a low power,
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
a versatile serial interface port. On the rising edge of CNV, the
AD7986 samples the voltage difference between the IN+ and
www.DataSheet.co.kr IN− pins. The voltages on these pins usually swing in opposite
phases between 0 V and VREF. It features a very high sampling
rate turbo mode (TURBO = high) and a reduced power normal
mode (TURBO = low) for low power applications where the
power is scaled with the throughput.
In normal mode (TURBO = low), the SPI-compatible serial
interface also features the ability, using the SDI input, to daisy-
chain several ADCs on a single 3-wire bus and provide an
optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V
using the separate VIO supply.
The AD7986 is available in a 20-lead LFCSP (QFN) with
operation specified from −40°C to +85°C.
Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs
Type
100 kSPS
250 kSPS
400 kSPS to 500 kSPS
14-Bit
AD7940
AD79421
AD79461
16-Bit
AD7680
AD76851
AD76861
AD7683
AD76871
AD76881
AD7684
AD7694
AD76931
18-Bit
AD76911
AD76901
≥1000 kSPS
AD79801
AD79831
AD79821
AD79841
AD7986
ADC Driver
ADA4941-1
ADA4841-x
ADA4941-1
ADA4841-x
AD8021
1 Pin-for-pin compatible.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
AD7986
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode)
Acquisition Time
Time Between Conversions (Turbo Mode/Normal Mode)
CNV Pulse Width (CS Mode)
Data Read During Conversion (Turbo Mode/Normal Mode)
Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
www.DataSheet.co.kr
Symbol
tCONV
tACQ
tCYC
tCNVH
tDATA
tQUIET
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ
100
500/660
10
20
9
11
3.5
3.5
2
4
0
0
5
5
2
3
Max
400/500
200/300
6
10
8
5
1 See Figure 2 and Figure 3 for load conditions.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
tDELAY
VIH1
VIL1
10% VIO
tDELAY
VIH1
VIL1
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. B | Page 5 of 28
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
100
99
98
97
96
95
94
93
92
91
90
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1
INPUT LEVEL (dB)
Figure 17. SNR vs. Input Level
3.0
IREF
2.5
0
2.0
IAVDD
1.5
IDVDD
1.0
IBVDD
0.5
IVIO
0
2.375
2.425
2.475
2.525
2.575
AVDD AND DVDD VOLTAGE (V)
Figure 18. Operating Currents vs. Supply Voltage
2.625
AD7986
3.0
IREF
2.5
2.0
IAVDD
1.5
1.0
0.5
IBVDD
0
–55 –35 –15 5 25 45 65 85 105
TEMPERATURE (C)
Figure 19. Operating Currents vs. Temperature
125
14
12
10
8
6
4
IAVDD + IDVDD + IVIO
2
www.DataSheet.co.kr
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 20. Power-Down Currents vs. Temperature
Rev. B | Page 11 of 28
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7986.PDF ] | |
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