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PDF A2V64S40CTP Data sheet ( Hoja de datos )
| Número de pieza | A2V64S40CTP | |
| Descripción | 64M Single Data Rate SDRAM | |
| Fabricantes | Powerchip | |
| Logotipo |  |
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Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Powerchip Semiconductor Corporation
A2V64S40CTP
64M Single Data Rate Synchronous DRAM
Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
CLK
CKE
Input
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), DEEP POWER DOWN (all banks idle), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CLK, are disabled during power-down and self
refresh modes, providing low standby power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
/CS
Input
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank
selection on systems with multiple banks. /CS is considered part of the command code.
/CAS, /RAS,
/WE
LDQM,
UDQM,
BA0, BA1
Input
Input
Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered
same state when referenced as DQM.
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Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also select between the mode register and
the extended mode register.
A0–A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (row address A0–A11) and
READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one
location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
DQ0–DQ15
NC
VDDQ
VSSQ
VDD
VSS
I/O Data Input/Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is recommended they be
– connected or VSS.
Supply
Supply
Supply
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Core Power Supply.
Ground.
Revision 1.0
Page 2/38
March, 2005
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Powerchip Semiconductor Corporation
A2V64S40CTP
64M Single Data Rate Synchronous DRAM
TRUTH TABLE
Command Truth Table
COMMAND
Symbol CKEn-1
Device deselect
DSL H
No operation
NOP
H
Burst stop
BST H
Read
RD H
Read with auto precharge
RDA
H
Write
WR H
Write with auto precharge
WRA
H
Bank activate
ACT
H
Precharge select bank
PRE
H
Precharge all banks
PALL
H
Mode register set
MRS
H
Extended mode register set
EMRS
H
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn
X
X
H
X
X
X
X
X
X
X
X
X
/CS
H
L
L
L
L
L
L
L
L
L
L
L
/RAS
X
H
H
H
H
H
H
L
L
L
L
L
/CAS
X
H
H
L
L
L
L
H
H
H
L
L
/WE
X
H
L
H
H
L
L
H
L
L
L
L
BA1
X
X
X
V
V
V
V
V
V
X
L
H
BA0
X
X
X
V
V
V
V
V
V
X
L
L
A10/A
P
X
X
X
L
H
L
H
V
L
H
L
L
A11,
A9 ~ A0
X
X
X
V
V
V
V
V
X
X
X
V
CKE Truth Table
Current state
Function
Activating
Clock suspend mode entry
Any Clock suspend mode
Clock suspend
Clock suspend mode exit
Idle Auto refresh command
Idle Self refresh entry
Idle Power down entry
Idle
Self refresh
Deep power down entry
Self refresh exit
Power down
Power down exit
Deep power down Deep power down exit
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Symbol
REF
SREF
PD
DPD
CKEn-1
H
L
L
H
H
H
H
H
www.DataSheet.co.kr
L
L
L
L
L
CKEn
L
L
H
H
L
L
L
L
H
H
H
H
H
/CS
X
X
X
L
L
L
H
L
L
H
L
H
X
/RAS
X
X
X
L
L
H
X
H
H
X
H
X
X
/CAS
X
X
X
L
L
H
X
H
H
X
H
X
X
/WE /Address
XX
XX
XX
HX
HX
HX
XX
LX
HX
XX
HX
XX
XX
Revision 1.0
Page 8/38
March, 2005
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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