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PDF AK4430 Data sheet ( Hoja de datos )
| Número de pieza | AK4430 | |
| Descripción | 192kHz 24-Bit Stereo DAC | |
| Fabricantes | AKM | |
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[AK4430]
AK4430
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4430 is 3.3V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4430 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4430 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as portable A/V players, set-top boxes, and digital televisions. The AK4430 is offered in
a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-bit MSB justified, I2S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
www.DataSheet.co.kr
128fs or 192fs (Quad Speed Mode)
THD+N: -91dB
Dynamic Range: 104dB
Automatic Power-on Reset Circuit
Power supply: +3.0 ∼ +3.6V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
SMUTE
DIF
Control
Interface
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
Clock
Divider
8X
Interpolator
8X
Interpolator
ΔΣ
Modulator
ΔΣ
Modulator
SCF
LPF
SCF
LPF
VDD
VREFH
2.2μ
VSS1
AOUTL
AOUTR
Charge
Pump
CP CN VEE VSS2
1μ 1μ
CVDD
MS1196-E-01
-1-
2011/03
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
[AK4430]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ, unless otherwise specified)
Parameter
min typ max
Resolution
24
Dynamic Characteristics (Note 5)
THD+N
fs=44.1kHz, BW=20kHz
fs=96kHz, BW=40kHz
fs=192kHz, BW=40kHz
Dynamic Range (-60dBFS with A-weighted, Note 6)
S/N (A-weighted, Note 7)
Interchannel Isolation (1kHz)
Interchannel Gain Mismatch
PSRR (Note 9)
- -91 -82
- -91 -
- -89 -
96 104
-
96 104
-
90 104
-
- 0.2 0.5
62
DC Accuracy
DC Offset (at output pin)
Gain Drift
Output Voltage (Note 8)
Load Capacitance (Note 10)
Load Resistance
-5 0 +5
- 100 -
1.85 2.0 2.15
- - 25
5- -
Power Supplies
Power Supply Current: (Note 11)
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (Note 12)
20 28
22 31
10 100
Note 5. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 6. 98dB for 16-bit input data
Note 7. S/N does not depend on input data length.
Note 8. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD
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AOUT (typ.@0dB) = 2Vrms × VDD/3.3.
Note 9. PSRR is applied to VDD and CVDD with 1kHz, 50mVpp.
Note 10. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 11. The current into VDD and CVDD.
Note 12. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD.
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
mV
ppm/°C
Vrms
pF
kΩ
mA
mA
μA
MS1196-E-01
-5-
2011/03
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
AK4430
AOUTR
(AOUTL)
0V
2Vrms
[AK4430]
Figure 6. Audio Signal Output
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission. In one cycle of LRCK, eight “H” pulses or more
must not be input to the SMUTE pin.
SMUTE pin
0dB
Attenuation
-∞
AOUT
1024/fs
(1)
1024/fs
www.DataSheet.co.kr
GD GD
(2)
(3)
Notes:
(1) The time for input data attenuation to -∞ is :
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to 0dB in the same cycle.
Figure 7. Soft Mute Function
MS1196-E-01
- 11 -
2011/03
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet AK4430.PDF ] | |
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