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PDF SSTL16857 Data sheet ( Hoja de datos )
| Número de pieza | SSTL16857 | |
| Descripción | 14-bit SSTL_2 registered driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
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SSTL16857
14-bit SSTL_2 registered driver with
differential clock inputs
Product specification
Supersedes data of 1999 Apr 29
1999 Sep 30
Philips
Semiconductors
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Philips Semiconductors
14-bit SSTL_2 registered driver with
differential clock inputs
Product specification
SSTL16857
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0_C to +70_C (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V UNIT
MIN MAX MIN MAX
fclock
Clock frequency
200 200 MHz
tw Pulse duration, CLK, CLK HIGH or LOW
1.0 1.0 ns
tsu Setup time
Data before CLK↑, CLK↓
RESET HIGH before CLK↑, CLK↓
0.8
0.8
0.9
ns
1.0
th Hold time
0.5 0.5 ns
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0_C to +70_C; VDDQ = 2.3 – 2.7V and VDDQ does not exceed VCC.
Class I, VREF = VTT = VDDQ x 0.5 and CL = 10pF (unless otherwise noted) (see Figure 1)
SYMBOL
FROM
(INPUT)
TO
(OUTPUT)
LIMITS
VCC = 2.5V ±0.2V
MIN MAX
LIMITS
VCC = 3.3V ±0.3V
MIN MAX
fmax
tPLH/tPHL
tPHL
Maximum clock frequency
CLK and CLK
RESET
200 200
Q 1.0 3.1 0.7 2.6
Q 2.0 5.0 1.4 4.0
UNIT
MHz
ns
ns
184/200-pin DDR SDRAM DIMM
www.DataSheet.co.kr
BACK SIDE
CBT CBT
CBT CBT
CBT
CBT
CBT
CBT CBT
CBT3857 (9)
FRONT SIDE
SSTL16857 SSTL16857
PCK857
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00393
1999 Sep 30
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SSTL16857.PDF ] | |
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