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PDF SSTL16877 Data sheet ( Hoja de datos )
| Número de pieza | SSTL16877 | |
| Descripción | 14-bit SSTL_2 registered driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SSTL16877 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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INTEGRATED CIRCUITS
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SSTL16877
14-bit SSTL_2 registered driver with
differential clock inputs
Product specification
Supersedes data of 2000 Apr 11
2000 Apr 20
Philips
Semiconductors
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Philips Semiconductors
14-bit SSTL_2 registered driver with
differential clock inputs
Product specification
SSTL16877
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0_C to +70_C (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 2.5 V ±0.2 V
MIN MAX
fclock
tw
tsu
Clock frequency
Pulse duration, CLK, CLK HIGH or LOW
Setup time
Data before CLK↑, CLK↓
RESET HIGH before CLK↑, CLK↓
1.0
0.2
0.8
200
th Hold time
1.2
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0_C to +70_C; VDDQ = 2.3 – 2.7 V and VDDQ does not exceed VCC.
Class I, VREF = VTT = VDDQ x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1)
SYMBOL
FROM
(INPUT)
TO
(OUTPUT)
LIMITS
VCC = 2.5 V ±0.2 V
MIN MAX
fmax
tPLH/tPHL
tPHL
Maximum clock frequency
CLK and CLK
RESET
200
Q 1.0 3.5
Q 2.0 4.0
184/200-pin DDR SDRAM DIMM
www.DataSheet.co.kr
BACK SIDE
CBT CBT
CBT CBT
CBT
CBT
CBT
CBT CBT
CBT3867 (9)
UNIT
MHz
ns
ns
ns
UNIT
MHz
ns
ns
FRONT SIDE
SSTL16877 SSTL16877
PCK877
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00502
2000 Apr 20
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SSTL16877.PDF ] | |
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