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PDF AT24C02C Data sheet ( Hoja de datos )
| Número de pieza | AT24C02C | |
| Descripción | EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT24C01C and AT24C02C
I2C-Compatible (2-wire) Serial EEPROM
1-Kbit (128 x 8), 2-Kbit (256 x 8)
DATASHEET
Features
Low-voltage Operation
̶ VCC = 1.7V to 5.5V
Internally Organized as 128 x 8 (1K) or 256 x 8 (2K)
I2C Compatible (2-wire) Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page Write Mode
̶ Partial Page Writes Allowed
Self-timed Write Cycle (5ms max)
High-reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Green Package Options (Pb/Halide-free/RoHS-compliant)
̶ 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 5-lead
SOT23, and 8-ball VFBGA
Die Sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C01C/02C provides 1024/2048-bits of Serial Electrically
Erasable and Programmable Read-Only Memory (EEPROM) organized as
128/256 words of eight bits each. Both devices include a cascading feature that
allows up to eight devices to share a common 2-wire bus. These devices are
optimized for use in many industrial and commercial applications where low
power and low voltage operation are essential. The AT24C01C/02C are available
in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN,
5-lead SOT23, and 8-ball VFBGA packages. In addition, the entire family
operates from 1.7V to 5.5V VCC.
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016
1 page  
4.3 AC Characteristics
Table 4-3. AC Characteristics
Applicable over recommended operating range from TAI = -40C to +85C, VCC = 1.7V to 5.5V, CL = 1TTL Gate and 100pF
(unless otherwise noted). Test conditions are listed in Note 2.
1.7V
2.5V, 5.0V
Symbol
Parameter
Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start.
400 1000
1.2 0.4
0.6 0.4
100 50
0.1 0.9 0.05 0.55
1.2 0.5
kHz
μs
μs
ns
μs
μs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
3.3V, +25C, Page Mode
0.6 0.25
μs
0.6 0.25
μs
00
μs
100 100
ns
0.3 0.3 μs
300 100 ns
0.6 .25
μs
50 50
ns
5 5 ms
1,000,000
Write Cycles
Note:
1. This parameter is ensured by characterization only.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.7V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5 VCC
AT24C01C/02C [DATASHEET]
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016
5
5 Page 
Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once
the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a Current Address Read
by sending a device address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a zero but does
generate a following stop condition.
Figure 9-2. Random Read
SDA LINE
S
T
A
R Device
T Address
M
S
B
WS
RT
IA
T Word R Device
E Address (n) T Address
RA
/C
WK
A
C
K
R
E
A
D
A
C
K
Dummy Write
Data (n)
S
T
O
P
N
O
A
C
K
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address
Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out sequential
data words. When the memory address limit is reached, the data word address will roll-over and the Sequential
Read will continue. The Sequential Read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition.
Figure 9-3. Sequential Read
Device
Address
R
E
A
D
SDA LINE
M RA
S /C
B WK
Data (n)
AA A
CC C
K Data (n + 1) K Data (n + 2) K
Data (n + x)
S
T
O
P
N
O
A
C
K
AT24C01C/02C [DATASHEET]
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AT24C02C.PDF ] | |
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