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부품번호 AD5686R 기능
기능 (AD5684R - AD5686R) Quad 16-/14-/12-Bit nanoDAC
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AD5686R 데이터시트, 핀배열, 회로
Data Sheet
Quad 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, I2C Interface
AD5696R/AD5695R/AD5694R
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696R/AD5695R/AD5694R family, are low power,
quad, 16-/14-/12-bit buffered voltage output DACs. The devices
include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). All devices operate from a single
2.7 V to 5.5 V supply, are guaranteed monotonic by design, and
exhibit less than 0.1% FSR gain error and 1.5 mV offset error
performance. The devices are available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
The AD5696R/AD5695R/AD5694R also incorporate a power-
on reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remain there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 µA at 3 V while in power-down mode.
The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial
interface that operates at clock rates up to 400 kHz, and
includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
A1
A0
AD5696R/AD5695R/AD5694R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
www.DataSheet.net/
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI Internal AD5686R
I2C Internal AD5696R
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5694R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696R (16-bit): ±2 LSB maximum
AD5695R (14-bit): ±1 LSB maximum
AD5694R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/




AD5686R pdf, 반도체, 판매, 대치품
AD5696R/AD5695R/AD5694R
Data Sheet
Parameter
REFERENCE OUTPUT
Output Voltage7
Reference TC8, 9
Output Impedance3
Output Voltage Noise3
Output Voltage Noise
Density3
Load Regulation Sourcing3
Load Regulation Sinking3
Output Current Load
Capability3
Line Regulation3
Long-Term Stability/Drift3
Thermal Hysteresis3
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
LOGIC OUTPUTS (SDA)3
Output Low Voltage, VOL
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
VDD
IDD
Normal Mode10
All Power-Down
Modes11
A Grade1
Min Typ Max
2.4975
2.5025
5 20
0.04
12
240
20
40
±5
100
12
125
25
0.7 × VLOGIC
2
±2
0.3 × VLOGIC
0.4
4
1.8
2.7
VREF + 1.5
5.5
3
5.5
5.5
0.59 0.7
1.1 1.3
14
6
B Grade1
Min Typ Max
2.4975
2.5025
25
0.04
12
240
20
40
±5
100
12
125
25
0.7 × VLOGIC
2
±2
0.3 × VLOGIC
0.4
4
1.8
2.7
VREF + 1.5
www.DataSheet.net/
0.59
1.1
1
5.5
3
5.5
5.5
0.7
1.3
4
6
Unit
V
ppm/°C
µV p-p
nV/√Hz
µV/mA
µV/mA
mA
µV/V
ppm
ppm
ppm
µA
V
V
pF
V
pF
V
µA
V
V
mA
mA
µA
µA
Test Conditions/Comments
At ambient
See the Terminology section
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
At ambient
At ambient
VDD ≥ 3 V
At ambient
After 1000 hours at 125°C
First cycle
Additional cycles
Per pin
ISINK = 3 mA
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
−40°C to +105°C
1 Temperature range: A and B grade: −40°C to +105°C.
2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696R), 64 to 16,320 (AD5695R), and 12 to 4080 (AD5694R).
3 Guaranteed by design and characterization; not production tested.
4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 31).
7 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
8 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
9 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
10 Interface inactive. All DACs active. DAC outputs unloaded.
11 All DACs powered down.
Rev. 0 | Page 4 of 32
Datasheet pdf - http://www.DataSheet4U.co.kr/

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AD5686R 전자부품, 판매, 대치품
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND1
SDA and SCL to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free (J-STD-020)
ESD2
FICDM
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +7 V
−40°C to +105°C
−65°C to +150°C
125°C
112.6°C/W
70°C/W
260°C
3.5 kV
1.5 kV
1 Excluding SDA and SCL.
2 Human body model (HBM) classification.
AD5696R/AD5695R/AD5694R
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
www.DataSheet.net/
Rev. 0 | Page 7 of 32
Datasheet pdf - http://www.DataSheet4U.co.kr/

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