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PDF AUIRS20302S Data sheet ( Hoja de datos )
| Número de pieza | AUIRS20302S | |
| Descripción | Automotive Grade | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Features
3 phase gate driver for 24V & higher drives
Under-voltage lockout for all channels
Cross-conduction prevention logic
High voltage pre-regulator MOSFET
Power-on reset architecture
FAULT detection and Reset
Current sense comparator
Over-current blanking time
3.3V logic compatible
Matched propagation delay for all channels
Fully operational up to +200V
Floating channels for bootstrap operation
High negative transients immunity
Pre-regulated supply line for uP
Automotive qualified
Leadfree, RoSH Compliant
Typical Applications
24V to 150V – 3 Phase Motor Drives
Automotive & Truck HVAC, PUMP
BLDC Motor Drives
Typical Connection Diagram
September 14th, 2011
Automotive Grade
AUIRS20302S
Pre-regulated Three Phase Gate Driver
Product Summary
Topology
VOFFSET
VOUT
Io+ & I o- (typical)
tON & tOFF (typical)
Deadtime (typical)
3-phase gate driver
200 V
8.0 V – 17 V
0.20 A & 0.35 A
530 ns / 530 ns
0.7 us
Package
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SOIC 28WB
+ Bat
5V Reg
ASIC
or uP
Ref
VCP
Vb1
Vb2
Vb3
VPR
Ho1
Ho2
Ho3
Vs1
Vs2
Vs3
AUIRS20302S
Flt
Frst
EN
Hin3
Lin3
Hin2
Lin2
Hin1
Lo1
Lo2
Lo3
Lin1
Vss Cap Can Com
UV
W
- Bat
www.irf.com
© 2009 International Rectifier
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
AUIRS20302S
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to VSS, all currents are defined positive into any lead. An operation above the absolute maximum limit is not implied and
could damage the part. The thermal resistance and power dissipation ratings are measured under board mounted and free air conditions
Symbol
VB1,2,3
VHO1,2,3
VS1,2,3
VPR
VCP
COM
VLO1,2,3, / FLT
VIN
Can/Cap
EN/Frst
dV/dt
RthJA
TJ
TS
TReflow
Definition
High side floating supply voltage
High side floating output voltage
High side offset voltage
Low side supply voltage
Charge pump output voltage
Power ground
Low side output voltage LO#; FLT pin
Input pin voltage (LIN#, HIN#,)
Over-current comparator inputs
Enable & Fault Reset inputs
High side floating voltage slew rate
Junction to ambient thermal resistance
Maximum operating junction temperature
Maximum storage temperature
Reflow max. temperature (60 sec.)
Min.
-0.3
VS1,2,3 - 0.3
VB 1,2,3 - 20
-0.3
-0.3
-5
-0.3
-0.3
-0.3
-0.3
—
—
-55
—
Max. Units
220
VB 1,2,3 + 0.3
VB 1,2,3 + 0.3
17
17
5
V
VPR + 0.3
VPR + 0.3
VPR + 0.3
VPR + 0.3
50
80
150
V/ns
°C/W
150 °C
260
Recommended Operating Conditions
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The Input/Output timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions.
All voltage parameters are referenced to VSS. The VS & COM offset rating are tested with all supplies biased at 15V differential.
Symbol
VB1,2,3
VHO 1,2,3
VS 1,2,3
VPR
VLO1,2,3
COM
VHO1,2,3
VLO1,2,3
VIN
Vcan/cap
VCP
Definition
High side floating supply voltage
High side output voltage HO#
High side floating supply voltage
Low side supply voltage
Low side output voltage LO#
Power ground
High side output voltage
Low side output voltage
Logic input voltage LIN, HIN, EN, CAp, CAn, FRST
Common mode voltage on the CAN & CAP inputs
Charge Pump Output Voltage
Min.
VS1,2,3 +6
VS1,2,3-0.3
(Note 1)
6
-0.3
-5
VS1,2,3
COM
VSS-0.3
0
-
Max.
VS1,2,3 +19
VB1,2,3+0.3
200
17
VPR+0.3
5
VB1,2,3
VPR
VPR
5
15
Units
V
Note 1: Logic operational for VS between COM -5V to COM +200V. Logic state held for VS of COM -5 to COM – VBS.
(Please refer to the Design Tip DT97 -3 for more details).
www.irf.com
© 2010 International Rectifier
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
AUIRS20302S
Application Information and Additional Details
Input Short-Pulse / Noise Rejection Filter
The inputs of this I.C are compatible with CMOS and TTL standards. The AUIRS20302S has been designed in order to
also interface the 3.3V logic signals. The VIN th+ and VIN th- thresholds of the input Schmitt trigger were set to 1.9V
and 1V (typical). Figure #1 shows the inner logic signal versus the input profile.
Figure 1: Input Thresholds
Figure 2: Input Filter
A filter is then implemented just after the Schmitt trigger on every input pin. HIN & LIN feature a 270 ns filter (typical)
while FRST & EN have a 50 ns one. Its principle greatly improves the input/output pulse symmetry as well as helps
reject noise spikes. The behaviour of the input filters is presented in the Figure #2. The parameter tFILIN represents the
minimum pulse duration to pass the filter.
Logic Control Block
This block centralizes all the logic signals in order to: Generatewww.DataSheet.net/ the proper Outputs drives with minimum dead-time
insertion, prevent shoot-through sequences, blank premature triggering of the short-circuit comparator and reset the
FAULT flag. The enable pin (EN) switches off all outputs immediately in case of an urgent system request. It actually
can be used to cycle the gates. The figure #3 shows all the signals timing.
Figure 3: Input/Output Timing Diagram
The AUIRS20302S features an embedded dead-time circuitry. It inserts a minimum time period in which both the high
and low side switches are forced OFF. By this mean and for each leg, each power switch is fully off before the next one
turns on. This dead-time is automatically inserted by the AUIRS20302S including when the command sequence does
www.irf.com
© 2010 International Rectifier
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AUIRS20302S.PDF ] | |
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