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PCA9621 데이터시트 PDF




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부품번호 PCA9621 기능
기능 65 mA 8-bit 2-wire bus output port
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PCA9621 데이터시트, 핀배열, 회로
PCA9621
65 mA 8-bit 2-wire bus output port
Rev. 1 — 9 March 2011
Product data sheet
1. General description
The PCA9621 is a monolithic CMOS integrated circuit for general purpose output drive
configurable from a 2-wire bus interface (including I2C-bus, SMBus, PMBus, and other
systems based on similar principles). Output ports have a 65 mA sink capability, making
them ideal for driving LEDs.
The state of the outputs is determined by a programmable 8-bit register which can be read
and written via signals from the 2-wire bus (e.g., I2C-bus or similar).
The 2-wire bus interface also has 30 mA Fast-mode Plus (Fm+) capability, and
consequently can be run in excess of 1 MHz or up to 4000 pF capacitance. As such, the
PCA9621 can be connected to other 2-wire devices across long cable connections.
It can be mixed with other Fast-mode Plus slaves in systems driven by Fm+ buffers or by
the PCA9646 (fully buffered 4-channel bus switch) to build large scale systems with
high-speed or high-capacitance drive capability, for example large scale LED displays or
controlled lighting.
2. Features and benefits
„ 8 individually selectable open-drain output ports
www.DataSheet.net/
„ 65 mA static sink capability on all output ports
„ Ports may be paralleled for up to 500 mA drive
„ Ideal for simple LED or general purpose output drive
„ Fast-mode Plus (30 mA, 4000 pF) 2-wire bus capability
„ Works with I2C-bus (Standard-mode, Fast-mode, and Fast-mode Plus), SMBus
(standard and high power mode), and PMBus
„ Fast switching times allow operation in excess of 1 MHz
„ Operating voltages from 2.7 V to 5.5 V
3. Applications
„ LED and 7-segment displays
„ Simple high-power (500 mA) LED dimming
„ General purpose output
„ Instrumentation indicators
Datasheet pdf - http://www.DataSheet4U.co.kr/




PCA9621 pdf, 반도체, 판매, 대치품
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7. Functional description
Refer to Figure 1 “Block diagram of PCA9621”.
7.1 VDD, VSS — DC supply pins
The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to
5.5 V. All other I/Os are clamped to VDD and VSS through ESD protection diodes.
7.2 SCL, SDA — 2-wire bus interface
The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I2C-bus style signalling. The interface is Fast-mode Plus
(Fm+) I2C-bus compatible, though the ports contain ESD protection diodes to the positive
and negative supplies. Consequently, VI2C-bus (voltage at SCL and SDA) must remain
within the VDD and VSS supply levels.
7.3 P0 to P7 — output ports
There are eight open-drain output ports whose state is determined by the Control register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.
Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.
www.DataSheet.net/
The ports are protected by ESD diodes to the supplies so they must not be driven above
the VDD or below the VSS levels.
7.4 RESET — reset IC to default state
The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET signal will clear the contents of the Control register, turning off all output
ports, and resetting the state of the I2C-bus slave transceiver block.
7.5 Power-On Reset (POR)
During power-on, the PCA9621 is internally held in the reset condition for a maximum of
trst = 500 ns. The default condition after reset is for the Control register to be erased
(all zeros), resulting in all output ports being off (high-impedance).
PCA9621
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2011
© NXP B.V. 2011. All rights reserved.
4 of 18
Datasheet pdf - http://www.DataSheet4U.co.kr/

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PCA9621 전자부품, 판매, 대치품
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
10. Characteristics
Table 4. Characteristics
Tamb = 40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
Power supply
VDD supply voltage
IDD supply current
I2C-bus ports (SCL, SDA)
operating
2.7 - 5.5 V
quiescent; VI (RESET pin) = 0 V;
VDD = 5.5 V
-
-1
μA
VI2C-bus
VIL
I2C-bus voltage
LOW-level input voltage
VIH HIGH-level input voltage
ILI input leakage current
VOL LOW-level output voltage
Open-drain output ports (P0 to P7)
SDA, SCL
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
pin at VDD or VSS
IOL = 30 mA; VDD = 2.7 V
IOL = 30 mA; VDD = 5.5 V
VSS 0.3
[1] -
[1] -
[1] 1.2
[1] 2.0
1
-
-
-
-
-
-
-
-
260
140
VDD + 0.3
0.4
0.5
-
-
+1
450
275
V
V
V
V
V
μA
mV
mV
IO(sink)
VOL
RESET
output sink current
LOW-level output voltage
LOW-level; port enabled
IOL = 65 mA
IOL = 100 μA
www.DataSheet.net/
65 - -
mA
-
440 725
mV
- 1 - mV
VIH HIGH-level input voltage
VIL LOW-level input voltage
Vhys hysteresis voltage
ILI input leakage current
tw(rst)L
LOW-level reset time
trst reset time
tPOR
power-on reset pulse time
Address pins (A0, A1, A2)
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
pin at VDD or VSS
VI < VIL
RESET pin; from VI > VIH
RESET pin; from VI > VIH
2.0
4.8
-
-
100
200
1
[2] -
-
-
--
--
- 650
- 900
--
--
- +1
25 -
250 500
250 500
V
V
mV
mV
mV
mV
μA
ns
ns
ns
VIH HIGH-level input voltage
VIL LOW-level input voltage
ILI input leakage current
Timing characteristics
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
pin at VDD or VSS
1.7 - -
V
3.5 - -
V
- - 0.7 V
- - 1.5 V
1 - +1 μA
tf fall time of both SDA and RPU = 200 Ω; measured from -
SCL signals
70 % VDD to 30 % VDD
tv(Q) data output valid time
[3] -
16 -
- 500
ns
ns
PCA9621
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2011
© NXP B.V. 2011. All rights reserved.
7 of 18
Datasheet pdf - http://www.DataSheet4U.co.kr/

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