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PDF M41T00AUD Data sheet ( Hoja de datos )
| Número de pieza | M41T00AUD | |
| Descripción | Serial real-time clock | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M41T00AUD
Serial real-time clock (RTC) with audio
Features
Combination real-time clock with audio
■ Serial real-time clock (RTC) based on M41T00
■ Audio section provides:
– 300 mW differential audio amplifier
– 256 and 512 Hz tone generation
– –33 to +12 dB gain, 3 dB steps (16 steps
plus MUTE)
■ 0 °C to 70 °C operation
■ Small DFN16 package (5 mm x 4 mm)
Real-time clock details
■ Superset of M41T00
■ 3.0 to 3.6 V operation
– Timekeeping down to 1.7 V
■ Automatic backup switchover circuit
– Ultra-low 400 nA backup current at 3.0 V
(typ)
– Suitable for battery or capacitor backup
– On-chip trickle charge circuit for backup
capacitor
■ 400 kHz I2C bus
■ M41T00 compatible register set with counters
for seconds, minutes, hours, day, date, month,
years, and century
– Automatic leap year compensation
– HT bit set when clock goes into backup
mode
■ RTC operates using 32,768 Hz quartz crystal
– Calibration register provides for
adjustments of –63 to +126 ppm
– Oscillator supports crystals with up to 40
kΩ series resistance, 12.5 pF load
capacitance
■ Oscillator fail detect circuit OF bit indicates
when oscillator has stopped for four or more
cycles
DFN16 (5 mm x 4 mm)
Audio section
■ Power amplifier
– Differential output amplifier
– Provides 300 mW into 8 Ω
(THD+N = 2% (max), fin = 1 kHz)
■ Summing node at audio input
– Inverting configuration with summing
www.DataSheet.net/ resistors into the minus (-) terminal
– 0 dB gain with 10 kΩ feedback resistor and
20 kΩ input summing resistors
– Signal input centered at VDD/2
– 1.6 VP-P analog input range (max)
■ 256 or 512 Hz signal multiplexing with analog
input to provide audio with beep tones
■ Volume control, 4-bit register
– Allows gain adjustment from –33 dB to
+12 dB
– 3 dB steps
– MUTE bit
■ Audio automatically shuts off in backup mode
February 2012
Doc ID 13480 Rev 5
1/42
www.st.com
1
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
M41T00AUD
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical hookup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Counter update diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Switchover thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trickle charge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Audio section diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DFN16 (5 mm x 4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DFN16 (5 mm x 4 mm) footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
www.DataSheet.net/
Doc ID 13480 Rev 5
5/42
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
M41T00AUD
Operation
4.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
● Bus not busy. Both data and clock lines remain high.
● Start data transfer. A change in the state of the data line, from high to low, while the
clock is high, defines the START condition.
● Stop data transfer. A change in the state of the data line, from low to high, while the
clock is high, defines the STOP condition.
● Data valid. The state of the data line represents valid data when after a start condition,
the data line is stable for the duration of the high period of the clock signal. The data on
the line may be changed during the low period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the message is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves".
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● Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Doc ID 13480 Rev 5
11/42
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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