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PDF LPC4357 Data sheet ( Hoja de datos )

Número de pieza LPC4357
Descripción (LPC4333 - LPC4357) 32-bit ARM Cortex-M4/M0 MCU
Fabricantes NXP Semiconductors 
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LPC4357/53/37/33
32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC
Rev. 2.1 — 4 September 2012
Preliminary data sheet
1. General description
The LPC4357/53/37/33 are ARM Cortex-M4 based microcontrollers for embedded
applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and
136 kB of on-chip SRAM, 16 kB of EEPROM memory, advanced configurable peripherals
such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO)
interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller,
and multiple digital and analog peripherals. The LPC4357/53/37/33 operate at CPU
frequencies of up to 204 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
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performance with a simple instruction set and reduced code size.
2. Features and benefits
Cortex-M4 Processor core
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 Processor core
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
application processor.
Running at frequencies of up to 204 MHz.
JTAG and built-in NVIC.
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LPC4357 pdf
NXP Semiconductors
LPC4357/53/37/33
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4357FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4357FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4353FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4353FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4337FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4337FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4337FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
LPC4337FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4333FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4333FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LPC4333FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
LPC4333FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
Version
SOT740-2
SOT570-3
SOT459-1
SOT740-2
SOT570-3
SOT459-1
SOT740-2
SOT570-3
SOT926-1
SOT486-1
SOT740-2
SOT570-3
SOT926-1
SOT486-1
4.1 Ordering options
Table 2. Ordering options
Type number
Flash Flash
bank A
Flash Total
bank B SRAM
LPC4357FET256
LPC4357FET180
LPC4357FBD208
LPC4353FET256
LPC4353FET180
LPC4353FBD208
LPC4337FET256
LPC4337FET180
LPC4337FET100
LPC4337FBD144
LPC4333FET256
LPC4333FET180
LPC4333FET100
LPC4333FBD144
1 MB
1 MB
1 MB
512 kB
512 kB
512 kB
1 MB
1 MB
1 MB
1 MB
512 kB
512 kB
512 kB
512 kB
512 kB
512 kB
512 kB
256 kB
256 kB
256 kB
512 kB
512 kB
512 kB
512 kB
256 kB
256 kB
256 kB
256 kB
512 kB
512 kB
512 kB
256 kB
256 kB
256 kB
512 kB
512 kB
512 kB
512 kB
256 kB
256 kB
256 kB
256 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
136 kB
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LCD
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
no
Ethernet
USB0
(Host,
Device,
OTG)
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
yes yes
USB1
(Host,
Device)/
ULPI
interface
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
ADC
GPIO
channels
8 164
8 118
8 142
8 164
8 118
8 142
8 164
8 118
4 49
8 83
8 164
8 118
4 49
8 83
LPC4357_53_37_33
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 4 September 2012
© NXP B.V. 2012. All rights reserved.
5 of 150
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LPC4357 arduino
NXP Semiconductors
Table 3. Pin description …continued
Pin name
LPC4357/53/37/33
32-bit ARM Cortex-M4/M0 microcontroller
Description
P1_5
P1_6
P1_7
R5 N3 J4
65 48 [2] N; I/O GPIO1[8] — General purpose digital input/output pin.
PU O CTOUT_10 — SCT output 10. Match output 3 of
timer 3.
- R — Function reserved.
O EMC_CS0 — LOW active Chip Select 0 signal.
I USB0_PWR_FAULT — Port power fault signal
indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry
required to detect over-current condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
O SD_POW — SD/MMC power monitor output.
T4 P3 K4 67 49 [2] N; I/O GPIO1[9] — General purpose digital input/output pin.
PU I CTIN_5 — SCT input 5. Capture input 2 of timer 2.
- R — Function reserved.
O EMC_WE — LOW active Write Enable signal.
- R — Function reserved.
O EMC_BLS0 — LOW active Byte Lane select signal 0.
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I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
T5 N4 G4 69 50 [2] N; I/O GPIO1[0] — General purpose digital input/output pin.
PU I U1_DSR — Data Set Ready input for UART1.
O CTOUT_13 — SCT output 13. Match output 3 of
timer 3.
I/O EMC_D0 — External memory data line 0.
O USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates
that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at
reset. This signal has opposite polarity compared to
the USB_PPWR used on other NXP LPC parts.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
LPC4357_53_37_33
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 4 September 2012
© NXP B.V. 2012. All rights reserved.
11 of 150
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