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부품번호 PCAL6408A 기능
기능 8-bit I2C-bus/SMBus I/O expander
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PCAL6408A 데이터시트, 핀배열, 회로
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
with interrupt output, reset, and configuration registers
Rev. 2 — 6 December 2012
Product data sheet
1. General description
The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I2C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL6408A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCAL6408A is provided through VDD(I2C-bus).
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VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates
the VDD level of the I2C-bus to the PCAL6408A, while the voltage level on Port P of the
PCAL6408A is determined by the VDD(P).
The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output,
and Polarity Inversion registers and additionally, the PCAL6408A has Agile I/O, which are
additional features specifically designed to enhance the I/O. These additional features
are: programmable output drive strength, latchable inputs, programmable
pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable
open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the
PCA6408A, however, the PCAL6408A powers up with all I/O interrupts masked. This
mask default allows for a board bring-up free of spurious interrupts at power-up.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete
components.
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PCAL6408A pdf, 반도체, 판매, 대치품
NXP Semiconductors
4. Block diagram
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
INT
ADDR
SCL
SDA
LP FILTER
INTERRUPT
LOGIC
PCAL6408A
INPUT
FILTER
I2C-BUS
CONTROL
SHIFT
REGISTER 8 BITS
I/O
PORT
P0 to P7
VDD(I2C-bus)
VDD(P)
RESET
VSS
POWER-ON
RESET
All I/Os are set to inputs at reset.
Fig 1. Block diagram (positive logic)
write pulse
read pulse
I/O control
002aah085
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PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 December 2012
© NXP B.V. 2012. All rights reserved.
4 of 48
datasheet pdf - http://www.DataSheet4U.net/

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PCAL6408A 전자부품, 판매, 대치품
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
6. Voltage translation
Table 4 shows how to set up VDD levels for the necessary voltage translation between the
I2C-bus and the PCAL6408A.
Table 4. Voltage translation
VDD(I2C-bus) (SDA and SCL of I2C master)
1.8 V
1.8 V
1.8 V
1.8 V
2.5 V
2.5 V
2.5 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
5V
5V
5V
5V
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VDD(P) (Port P)
1.8 V
2.5 V
3.3 V
5V
1.8 V
2.5 V
3.3 V
5V
1.8 V
2.5 V
3.3 V
5V
1.8 V
2.5 V
3.3 V
5V
7. Functional description
Refer to Figure 1 “Block diagram (positive logic)”.
7.1 Device address
The address of the PCAL6408A is shown in Figure 5.
slave address
0 1 0 0 0 0 AD R/W
DR
fixed
programmable
002aaf539
Fig 5. PCAL6408A address
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address defines the operation (read or write) to be performed. A HIGH (logic 1) selects a
read operation, while a LOW (logic 0) selects a write operation.
PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 December 2012
© NXP B.V. 2012. All rights reserved.
7 of 48
datasheet pdf - http://www.DataSheet4U.net/

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부품번호상세설명 및 기능제조사
PCAL6408A

8-bit I2C-bus/SMBus I/O expander

NXP Semiconductors
NXP Semiconductors

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