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BU-61581 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BU-61581
기능 (BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT
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BU-61581 데이터시트, 핀배열, 회로
BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
ACE User’s Guide
Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal
(BC/RT/MT)
Advanced
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
“glue” logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The ACE series is packaged in a 1.9 -
square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
The advanced functional architecture
of the ACE terminals provides soft-
ware compatibility to DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RThttp://www.DataSheet4U.net/
address (hardwired is standard) and
external transmitter inhibit inputs.
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory
Interface
Standard 4K x 16 RAM and
Optional 12K x 16 or 8K x 17 RAM
Available
Optional RAM Parity
Generation/Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable Illegalization
Selective Message Monitor
Simultaneous RT/Monitor Mode
CH. A
TX/RX_A
TRANSCEIVER
A
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
*SHARED
RAM
DATA BUS
ADDRESS BUS
DATA
BUFFERS
ADDRESS
BUFFERS
D15-D0
A15-A0
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
RT ADDRESS
MISCELLANEOUS
TX/RX_B
RTAD4-RTAD0, RTADP
INCMD
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
PROCESSOR
AND
MEMORY
CONTROL
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
INT INTERRUPT
REQUEST
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM
© 1992, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/




BU-61581 pdf, 반도체, 판매, 대치품
Notes for Table 1: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65170/61580XX hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535µs minus message time), in
increments of 1µs.
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5V logic and transceiver. +5V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-
cal to the specifications for the BU-65170, BU-61580, and BU-
61585 respectively.
INTRODUCTION
DDC's ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9-square-inch,
70-pin DIP or surface mountable flatpack or J-lead package, the
ACE series contains dual low-power transceivers and
encoder/decoders, complete BC/RT/MT multi-protocol logic,
memory management and interrupt logic, 4K x 16 of shared sta-
tic RAM and a direct, buffered interface to a host processor bus.
The BU-65170/61580 contains internal address latches and bidi-
rectional data buffers to provide a direct interface to a host
processor bus. The BU-65170/61580 may be interfaced directly
to both 16-bit and 8-bit microprocessors in a buffered shared
RAM configuration. In addition, the ACE may connect to a 16-bit
processor bus via a Direct Memory Access (DMA) interface. The
BU-65170/61580 includes 4K words of buffered RAM.
Alternatively, the ACE may be interfaced to as much as 64K
words of external RAM in either the shared RAM or DMA config-
urations.
The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,
MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),
and the McAir A3818, A5232, and A5690 protocols. Full compli-
ance to the McAir specs, however, requires the use of a sinu-
soidal transceiver (transceiver option 5). Refer to the BU-61590
data sheet for additional information on McAir terminals.
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The ACE series implements three monitor modes: a word moni-
tor, a selective message monitor, and a combined RT/selective
monitor. Other features include options for automatic retries and
programmable intermessage gap for BC mode, an internal Time
Tag Register, an Interrupt Status Register and internal command
illegalization for RT mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
The transceivers in the BU-65170/61580X3(X6) are fully mono-
lithic, requiring only a +5 volt power input. Besides eliminating
the need for an additional power supply, the use of a 5 volt (only)
transceiver requires the use of step-up, rather than step-down,
isolation transformers. This provides the advantage of a higher
terminal input impedance than is possible for a 15 volt or 12 volt
transmitter. As a result, there is greater margin for the input
impedance test, mandated for 1553 validation testing. This
allows for longer cable lengths between an LRU's system con-
nector and the isolation transformers of an embedded 1553 ter-
minal.
For the +5 V and -15 V/-12 V front end, the BU-65170/
61580X1(X2) uses low-power bipolar analog monolithic and
thick-film hybrid technology. The transceiver requires +5 V and -
15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-
age source transmitters. The voltage source transmitters provide
superior line driving capability for long cables and heavy
amountshttp://www.DataSheet4U.net/ of bus loading. In addition, the monolithic transceivers
in the BU-65170/61580X1 provide a minimum stub voltage level
of 20 volts peak-to-peak transformer coupled, making them suit-
able for MIL-STD-1760 applications.
The receiver sections of the BU-65170/61580 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage protec-
tion, threshold, common mode rejection, and word error rate. In
addition, the receiver filters have been designed for optimal oper-
ation with the J´ chip's Manchester II decoders.
J´ DIGITAL MONOLITHIC
The J´ digital monolithic represents the cornerstone element of
the ACE family of terminals. The development of the J´ chip rep-
resents the fifth generation of 1553 protocol and interface design
for DDC. Over the years, DDC's 1553 protocol and interface
design has evolved from: (1) discrete component sets, consisting
of multiple hybrids (with large numbers of chips inside the indi-
vidual hybrids) and programmable logic devices, to (2) multiple
custom ASICs to perform the functions of encoder/decoder and
RT protocol within a single hybrid, to (3) the BUS-61553
Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in
addition to a dual monolithic/thick-film transceiver and discrete
RAM chips, a custom protocol chip and a separate custom mem-
ory management/processor interface chip, to (4) the BUS-61559
Advanced Integrated Mux Hybrids with Enhanced RT Features
(AIM-HY'er — the AIM-HY'er series includes memory manage-
ment and processor interface functions beyond those of the AIM-
HY series) , to (5) the full integration of the J´ chip.
Data Device Corporation
www.ddc-web.com
4
BU-65170/61580/61585
H1 web-09/02-0
datasheet pdf - http://www.DataSheet4U.net/

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BU-61581 전자부품, 판매, 대치품
TABLE 4. CONFIGURATION REGISTER #1 (READ/WRITE 01H)
BIT
BC FUNCTION (Bits
11-0 Enhanced Mode Only)
RT WITHOUT ALTERNATE
STATUS
RT WITH ALTERNATE
MONITOR FUNCTION
STATUS (Enhanced Only) (Enhanced mode only bits 12-0)
15 RT/BC-MT (logic 0)
(MSB)
(logic 1)
(logic 1)
(logic 0)
14 MT/BC-RT (logic 0)
(logic 0)
(logic 0)
(logic 1)
13 CURRENT AREA B/A
12 MESSAGE STOP-ON-ERROR
CURRENT AREA B/A
CURRENT AREA A/B
MESSAGE MONITOR ENABLED MESSAGE MONITOR
(MMT)
ENABLED (MMT)
CURRENT AREA B/A
MESSAGE MONITOR ENABLED
(MMT)
11 FRAME STOP-ON-ERROR
DYNAMIC BUS CONTROL
ACCEPTANCE
S10
TRIGGER ENABLED WORD
10 STATUS SET STOP-ON-MESSAGE BUSY S09 START-ON-TRIGGER
9 STATUS SET STOP-ON-FRAME SERVICE REQUEST
S08
STOP-ON-TRIGGER
8 FRAME AUTO-REPEAT
SUBSYSTEM FLAG
S07
NOT USED
7 EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) S06
EXTERNAL TRIGGER ENABLED
6 INTERNAL TRIGGER ENABLED NOT USED
S05
NOT USED
5
INTERMESSAGE GAP TIMER
NOT USED
ENABLED
S04
NOT USED
4 RETRY ENABLED
NOT USED
S03
NOT USED
3 DOUBLED/SINGLE RETRY
NOT USED
S02
NOT USED
2 BC ENABLED (Read Only)
NOT USED
S01
MONITOR ENABLED(Read Only)
1
0
(LSB)
BC FRAME IN PROGRESS (Read
Only)
BC MESSAGE IN PROGRESS
(Read Only)
NOT USED
S00
MONITOR TRIGGERED
(Read Only)
http://www.DataSheet4U.net/
RT MESSAGE IN PROGRESS RT MESSAGE IN PROGRESS MONITOR ACTIVE
(Enhanced mode only,Read Only) (Read Only)
(Read Only)
TABLE 5. CONFIGURATION REGISTER #2 (READ/WRITE 02h)
BIT DESCRIPTION
15(MSB) ENHANCED INTERRUPTS
14 RAM PARITY ENABLE (BU-61585/6 AND BU-65621 ONLY)
13 BUSY LOOKUP TABLE ENABLE
12 RX SA DOUBLE BUFFER ENABLE
11 OVERWRITE INVALID DATA
10 256-WORD BOUNDARY DISABLE
9 TIME TAG RESOLUTION 2(TTR2)
8 TIME TAG RESOLUTION 1 (TTR1)
7 TIME TAG RESOLUTION 0 (TTR0)
6 CLEAR TIME TAG ON SYNCHRONIZE
5 LOAD TIME TAG ON SYNCHRONIZE
4 INTERRUPT STATUS AUTO CLEAR
3 LEVEL/PULSE* INTERRUPT REQUEST
2 CLEAR SERVICE REQUEST
1 ENHANCED RT MEMORY MANAGEMENT
0(LSB) SEPARATE BROADCAST DATA
TABLE 6. START/RESET REGISTER (WRITE 03H)
BIT DESCRIPTION
15(MSB) RESERVED
••
••
••
7 RESERVED
6 BC/MT STOP-ON-MESSAGE
5 BC STOP-ON-FRAME
4 TIME TAG TEST CLOCK
3 TIME TAG RESET
2 INTERRUPT RESET
1 BC/MT START
0(LSB) RESET
Data Device Corporation
www.ddc-web.com
7
BU-65170/61580/61585
H1 web-09/02-0
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부품번호상세설명 및 기능제조사
BU-61580

(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

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DDC
BU-61581

(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

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