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부품번호 BU-61582
기능 SPACE LEVEL MIL-STD-1553 BC/RT/MT
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BU-61582 데이터시트, 핀배열, 회로
BU-61582
SPACE LEVEL MIL-STD-1553 BC/RT/MT
ADVANCED COMMUNICATION
ENGINE (SP’ACE) TERMINAL
DESCRIPTION
DDC’s BU-61582 Space Advanced Communication Engine (SP’ACE)
is a radiation hardened version of the BU-61580 ACE terminal. DDC
supplies the BU-61582 with enhanced screening for space and other
high reliability applications.
The BU-61582 provides a complete integrated BC/RT/MT interfacehttp://www.DataSheet4U.net/
between a host processor and a MIL-STD-1553 bus. The BU-61582
maintains functional and software compatibility with the standard BU-
61580 product and is packaged in the same 1.9 square-inch package
footprint.
As an option, DDC can supply the BU-61582 with space level screen-
ing. This entails enhancements in the areas of element evaluation and
screening procedures for active and passive elements, as well as the
manufacturing and screening processes used in producing the termi-
nals.
The BU-61582 integrates dual transceiver, protocol, memory man-
agement and processor interface logic, and 16K words of RAM in the
choice of 70-pin DIP or flat pack packages. Transceiverless versions
may be used with an external electrical or fiber optic transceiver.
To minimize board space and ‘glue’ logic, the SP’ACE terminals pro-
vide ultimate flexibility in interfacing to a host processor and inter-
nal/external RAM.
Make sure the next
Card you purchase
has...
®
FEATURES
Radiation-Hardened to 1 MRad
Fully Integrated 1553 Terminal
Flexible Processor Interface
16K x 16 Internal RAM
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Intelligent RT Data Buffering
Small Ceramic Package
Available to SMD 5962-96887
Multiple Ordering Options;
+5V (Only)
+5V/-15V
+5V/-12V
+5V/Transceiverless
+5V (Only, with Transmit Inhibits)
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/




BU-61582 pdf, 반도체, 판매, 대치품
TABLE 1. SP’ACE SERIES SPECIFICATIONS (CONT)
PARAMETER
MIN TYP MAX UNITS
CLOCK INPUT
Frequency
„ Nominal Value (programmable)
• Default Mode
• Option
„ Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
„ Short Term Tolerance,1 second
• 1553A Compliance
• 1553B Compliance
„ Duty Cycle
• 16 MHz
• 12 MHz
16.0 MHz
12.0 MHz
0.01 %
0.1 %
0.001 %
0.01 %
33 67 %
40 60 %
1553 MESSAGE TIMING
Completion of CPU Write (BC Start-
to-Start of Next Message)
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout (Note 9)
„ 18.5 nominal
„ 22.5 nominal
„ 50.5 nominal
„ 128.0 nominal
Transmitter Watchdog Timeout
RT Response Timeout (Note 11)
17.5
21.5
49.5
128
4
2.5
10.5
18.5
22.5
50.5
129.5
668
6.5
19.5
23.5
51.5
131
9
µs
µs
µs
µs
µs
µs
µs
µs
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θJC)
„ BU-61582X0
4.6 °C/W
„ BU-61582X1
7.2 °C/W
„ BU-61582X2
7.2 °C/W
„ BU-61582X3/X6
12 °C/W
Operating Junction Temperature
-55
150 °C
Storage Temperature
-65 150 °C
Lead Temperature (soldering, 10 sec.)
+300 °C
PHYSICAL CHARACTERISTICS
Size
„ 70-pin DIP, Flat Pack
J-Lead, Gull Leads
Weight
„ 70-pin DIP, Flat Pack
J-Lead, Gull Leads
1.9 X 1.0 X 0.215 in.
(48.26 x 25.4 x 5.46 (mm)
0.6 oz
(7) (g)
TABLE 1 NOTES: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the SP'ACE Series hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed, but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535 µs minus message time), in
increments of 1 µs.
TABLE 1 NOTES (cont)
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5 V logic and transceiver. +5 V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
INTRODUCTION
DDC’s SP’ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9 square inch 70-
pin DIP, surface mountable Flat Pack or Gull Lead, the SP’ACE
series contains dual low-power transceivers and
encoder/decoders, complete BC/RT/MT multiprotocol logic,
memory management and interrupt logic, 16K X 16 of shared
static RAM and a direct, buffered interface to a host processor
bus.
The BU-61582 contains internal address latches and bidirection-
al data buffers to provide a direct interface to a host processor
bus. The BU-61582 may be interfaced directly to both 16-bit and
8-bit microprocessors in a buffered shared RAM configuration. In
addition, the SP’ACE may connect to a 16-bit processor bus via
http://www.DataSheet4U.net/
a Direct Memory Access (DMA) interface. The BU-61582
includes 16K words of buffered RAM. Alternatively, the SP’ACE
may be interfaced to as much as 64k words of external RAM in
either the shared RAM or DMA configurations.
The SP’ACE RT mode is multiprotocol, supporting MIL-STD-
1553A, MIL-STD-1553B Notice 2, and STANAG 3838 (including
EFAbus).
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The SP’ACE series implements three monitor modes: a word
monitor, a selective message monitor, and a combined RT/selec-
tive monitor.
Other features include options for automatic retries and pro-
grammable intermessage gap for BC mode, an internal Time Tag
Register, an Interrupt Status Register and internal command ille-
galization for RT mode.
Data Device Corporation
www.ddc-web.com
4
BU-61582
M-08/04-0
datasheet pdf - http://www.DataSheet4U.net/

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BU-61582 전자부품, 판매, 대치품
ADDRESSING, INTERNAL REGISTERS, AND MEMORY
MANAGEMENT
The software interface of the BU-61582 to the host processor
consists of 17 internal operational registers for normal operation,
an additional 8 test registers, plus 64K X 16 of shared memory
address space. The BU-61582’s 16K X 16 of internal RAM
resides in this address space. Reference TABLE 4.
Definition of the address mapping and accessibility for the
SP’ACE’s 17 nontest registers, and the test registers, is as fol-
lows:
Interrupt Mask Register:
Used to enable and disable interrupt requests for various condi-
tions.
Configuration Registers #1 and #2:
Used to select the BU-61582’s mode of operation, and for soft-
ware control of RT Status Word bits, Active Memory Area, BC
Stop-on-Error, RT Memory Management mode selection, and
control of the Time Tag operation.
Start/Reset Register:
Used for “command” type functions, such as software reset,
BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag
Register Test. The Start/Reset Register includes provisions for
stopping the BC in its auto-repeat mode, either at the end of the
current message or at the end of the current BC frame.
BC/RT Command Stack Pointer Register:
Allows the host CPU to determine the pointer location for the cur-
rent or most recent message when the BU-61582 is in BC or RT
modes.
BC Control Word/RT Subaddress Control Word
Register:
In BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the SP’ACE hybrid.
TABLE 4. ADDRESS MAPPING
ADDRESS LINES
REGISTER
DESCRIPTION/ACCESSIBILITY
HEX A4 A3 A2 A1 A0
00 0 0 0 0 0 Interrupt Mask Register (RD/WR)
01 0 0 0 0 1 Configuration Register #1 (RD/WR)
02 0 0 0 1 0 Configuration Register #2 (RD/WR)
03 0 0 0 1 1 Start/Reset Register (WR)
03
0
0
0
1
1
BC/RT Command Stack Pointer Register
(RD)
04
0
0
1
0
0
BC Control Word/RT Subaddress Control
Word Register (RD/WR)
05 0 0 1 0 1 Time Tag Register (RD/WR)
06 0 0 1 1 0 Interrupt Status Register (RD)
07 0 0 1 1 1 Configuration Register #3 (RD/WR)
08 0 1 0 0 0 Configuration Register #4 (RD/WR)
09 0 1 0 0 1 Configuration Register #5 (RD/WR)
0A 0 1 0 1 0 Data Stack Address Register (RD/WR)
0B
0
1
0
1
1
BC Frame Time Remaining Register
(RD/WR)
0C
0
1
1
0
0
BC Time Remaining to Next Message
Register (RD/WR)
0D
0
1
1
0
1
BC Frame Time/RT Last Command
/MT Trigger Word Register (RD/WR)
0E 0 1 1 1 0 RT Status Word Register (RD)
0F 0 1 1 1 1 RT BIT Word Register (RD)
10 1 0 0 0 0 Test Mode Register 0http://www.DataSheet4U.net/
17 1 0 1 1 1 Test Mode Register 7
18 1 1 0 0 0 reserved
1F 1 1 1 1 1 reserved
oscillator to clock the Time Tag Register. Start-of-Message
(SOM) and End-of-Message (EOM) sequences in BC, RT, and
Message Monitor modes cause a write of the current value of
the Time Tag Register to the stack area of RAM.
Time Tag Register:
Maintains the value of a real-time clock. The resolution of this
register is programmable from among 2, 4, 8, 16, 32, and 64
µs/LSB. The TAG_CLK input signal also may cause an external
Interrupt Status Register:
Mirrors the Interrupt Mask Register and contains a Master
Interrupt bit. It allows the host processor to determine the cause
of an interrupt request by means of a single READ operation.
Data Device Corporation
www.ddc-web.com
7
BU-61582
M-08/04-0
datasheet pdf - http://www.DataSheet4U.net/

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