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부품번호 UM10204
기능 I2C-bus specification and user manual
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UM10204 데이터시트, 핀배열, 회로
UM10204
I2C-bus specification and user manual
Rev. 4 — 13 February 2012
User manual
Document information
Info Content
Keywords
I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Abstract
Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I2C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
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up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.
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UM10204 pdf, 반도체, 판매, 대치품
NXP Semiconductors
UM10204
I2C-bus specification and user manual
Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
On-chip filtering rejects spikes on the bus data line to preserve data integrity.
The number of ICs that can be connected to the same bus is limited only by a
maximum bus capacitance. More capacitance may be allowed under some
conditions. Refer to Section 7.2.
Figure 1 shows an example of I2C-bus applications.
I2C
A/D or D/A
Converters
I2C
General Purpose
I/O Expanders
I2C
LED Controllers
I2C
DIP Switches
VDD4
VDD2
I2C
Multiplexers
and Switches
VDD0
PCA9541
I2C
Master Selector/
Demux
VDD1
I2C
Repeaters/
Hubs/Extenders
VDD5
I2C Port
via HW or
Bit Banging
MCUs
I2C
Bus Controllers
8
MCUs
I2C
Slave
VDD3
I2C
Serial EEPROMs
LCD Drivers
(with I2C)
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I2C
Real Time Clock/
Calendars
Fig 1. Example of I2C-bus applications
I2C
Temperature
Sensors
Bridges
(with I2C)
SPI
UART
USB
002aac858
2.1 Designer benefits
I2C-bus compatible ICs allow a system design to progress rapidly directly from a
functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be
modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I2C-bus compatible ICs that are particularly attractive to
designers:
Functional blocks on the block diagram correspond with the actual ICs; designs
proceed rapidly from block diagram to final schematic.
No need to design bus interfaces because the I2C-bus interface is already integrated
on-chip.
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 13 February 2012
© NXP B.V. 2012. All rights reserved.
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UM10204 전자부품, 판매, 대치품
NXP Semiconductors
UM10204
I2C-bus specification and user manual
UM10204
User manual
MICRO -
CONTROLLER
A
LCD
DRIVER
STATIC
RAM OR
EEPROM
SDA
SCL
GATE
ARRAY
ADC
MICRO -
CONTROLLER
B
mbc645
Fig 2. Example of an I2C-bus configuration using two microcontrollers
This example highlights the master-slave and receiver-transmitter relationships found on
the I2C-bus. Note that these relationships are not permanent, but only depend on the
direction of data transfer at that time. The transfer of data would proceed as follows:
1. Suppose microcontroller A wants to send information to microcontroller B:
microcontroller A (master), addresses microcontroller B (slave)
microcontroller A (master-transmitter), sends data to microcontroller B
(slave-receiver)
microcontroller A terminates the transfer.
2. If microcontroller A wants to receivehttp://www.DataSheet4U.net/ information from microcontroller B:
microcontroller A (master) addresses microcontroller B (slave)
microcontroller A (master-receiver) receives data from microcontroller B
(slave-transmitter)
microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the
transfer.
The possibility of connecting more than one microcontroller to the I2C-bus means that
more than one master could try to initiate a data transfer at the same time. To avoid the
chaos that might ensue from such an event, an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus.
If two or more masters try to put information onto the bus, the first to produce a ‘one’ when
the other produces a ‘zero’ loses the arbitration. The clock signals during arbitration are a
synchronized combination of the clocks generated by the masters using the wired-AND
connection to the SCL line (for more detailed information concerning arbitration see
Section 3.1.8).
Generation of clock signals on the I2C-bus is always the responsibility of master devices;
each master generates its own clock signals when transferring data on the bus. Bus clock
signals from a master can only be altered when they are stretched by a slow slave device
holding down the clock line or by another master when arbitration occurs.
Table 2 summarizes the use of mandatory and optional portions of the I2C-bus
specification and which system configurations use them.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 13 February 2012
© NXP B.V. 2012. All rights reserved.
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