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부품번호 UM10360
기능 LPC17xx User manual
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UM10360 데이터시트, 핀배열, 회로
UM10360
LPC17xx User manual
Rev. 01 — 4 January 2010
User manual
Document information
Info Content
Keywords
LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759,
LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3,
32-bit, USB, Ethernet, CAN, I2S, Microcontroller
Abstract
LPC17xx user manual
http://www.DataSheet4U.net/
datasheet pdf - http://www.DataSheet4U.net/




UM10360 pdf, 반도체, 판매, 대치품
NXP Semiconductors
UM10360
Chapter 1: LPC17xx Introductory information
2. Features
Refer to Section 1–4.1 for details of features on specific part numbers.
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
Up to 64 kB on-chip SRAM includes:
Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, Generalhttp://www.DataSheet4U.net/ Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Serial interfaces:
Ethernet MAC with RMII interface and dedicated DMA controller.
USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
Two-channel CAN controller.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
SPI controller with synchronous, serial, full duplex communication and
programmable data length. SPI is included as a legacy peripheral and can be used
instead of SSP0.
Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
4 of 835
datasheet pdf - http://www.DataSheet4U.net/

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UM10360 전자부품, 판매, 대치품
NXP Semiconductors
UM10360
Chapter 1: LPC17xx Introductory information
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC1769FBD100
LPC1768FBD100
LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
LPC1766FBD100
LPC1765FBD100
LPC1764FBD100
LPC1759FBD80
LPC1758FBD80
LPC1756FBD80
LQFP80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
LPC1754FBD80
LPC1752FBD80
LPC1751FBD80
Version
SOT407-1
SOT315-1
4.1 Part options summary
Table 2. Ordering options for LPC17xx parts
Type number
Max. CPU Flash
speed
Total
SRAM
LPC1769FBD100 120 MHz 512 kB 64 kB
LPC1768FBD100 100 MHz 512 kB 64 kB
LPC1767FBD100 100 MHz 512 kB 64 kB
LPC1766FBD100 100 MHz 256 kB 64 kB
LPC1765FBD100 100 MHz 256 kB 64 kB
LPC1764FBD100 100 MHz 128 kB 32 kB
LPC1759FBD80 120 MHz 512 kB 64 kB
LPC1758FBD80 100 MHz 512 kB 64 kB
LPC1756FBD80 100 MHz 256 kB 32 kB
LPC1754FBD80 100 MHz 128 kB 32 kB
LPC1752FBD80 100 MHz 64 kB 16 kB
LPC1751FBD80 100 MHz 32 kB 8 kB
Ethernet USB
http://www.DataSheet4U.net/
CAN I2S
yes
Device/Host/OTG 2
yes
yes
Device/Host/OTG 2
yes
yes no
no yes
yes
Device/Host/OTG 2
yes
no
Device/Host/OTG 2
yes
yes Device
2 no
no
Device/Host/OTG 2
yes
yes
Device/Host/OTG 2
yes
no
Device/Host/OTG 2
yes
no
Device/Host/OTG 1
no
no Device
1 no
no Device
1 no
DAC Package
yes 100 pin
yes 100 pin
yes 100 pin
yes 100 pin
yes 100 pin
no 100 pin
yes 80 pin
yes 80 pin
yes 80 pin
yes 80 pin
no 80 pin
no 80 pin
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
7 of 835
datasheet pdf - http://www.DataSheet4U.net/

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UM10360

LPC17xx User manual

NXP Semiconductors
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