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부품번호 UM10601
기능 LPC800 User manual
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UM10601 데이터시트, 핀배열, 회로
UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012
Preliminary user manual
Document information
Info
Keywords
Content
ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
Abstract
LPC800 Preliminary user manual
http://www.DataSheet4U.net/
datasheet pdf - http://www.DataSheet4U.net/




UM10601 pdf, 반도체, 판매, 대치품
NXP Semiconductors
UM10601
Chapter 1: LPC800 Introductory information
CRC engine.
Windowed Watchdog timer
Analog peripherals:
Comparator with external voltage reference with pin functions assigned through
the switch matrix.
Internal reference voltage.
Serial interfaces:
Three UART interfaces with pin functions assigned through the switch matrix.
Two SPI controllers with pin functions assigned through the switch matrix.
One I2C-bus interface with open-drain full I2C spec fast Modeplus.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the external clock input (CLKIN), the
system oscillator, or the internal RC oscillator.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes (Sleep,http://www.DataSheet4U.net/ deep-sleep, power-down, deep power-down).
Power-On Reset (POR).
Brownout detect.
Unique device serial number for identification.
Single power supply.
Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
4 of 313
datasheet pdf - http://www.DataSheet4U.net/

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UM10601 전자부품, 판매, 대치품
NXP Semiconductors
UM10601
Chapter 1: LPC800 Introductory information
1.5 General description
1.5.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000.
The core includes a single-cycle multiplier and a system tick timer (SysTick).
http://www.DataSheet4U.net/
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
7 of 313
datasheet pdf - http://www.DataSheet4U.net/

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UM10601

LPC800 User manual

NXP Semiconductors
NXP Semiconductors

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