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PDF ADP198 Data sheet ( Hoja de datos )
| Número de pieza | ADP198 | |
| Descripción | High-Side Load Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Logic Controlled, 1 A, High-Side Load
Switch with Reverse Current Blocking
ADP198
FEATURES
Low RDSON of 50 mΩ @ 3.3 V (WLCSP only)
Low input voltage range: 1.65 V to 6.5 V
1 A continuous operating current
Built-in level shift for control logic that can be operated by
1.2 V logic
Low 2.5 μA quiescent current @ VIN = 2.8 V
Low 1.1 μA shutdown current @ VIN = 2.8 V
Reverse current blocking
Programmable start-up time
Ultrasmall 1 mm × 1 mm, 4-ball, 0.5 mm pitch (WLCSP)
Tiny 8-lead lead frame chip scale package (LFCSP)
2.0 mm × 2.0 mm × 0.55 mm, 0.5 mm pitch
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
GENERAL DESCRIPTION
The ADP198 is a high-side load switch designed for operation
between 1.65 V and 6.5 V that is protected against reverse
current flow from output to input. A load switch provides power
domain isolation, thereby helping to keep subsystems isolated and
powered independently and enabling reduced power consumption.
The ADP198 contains a low on-resistance P-channel MOSFET
that supports more than 1 A of continuous load current. The
low 2.5 μA quiescent current and ultralow shutdown current
make the ADP198 ideal for battery-operated portable
TYPICAL APPLICATION CIRCUITS
ADP198
VIN
+
GND
REVERSE
POLARITY
PROTECTION
VOUT
EN
ON
OFF
LEVEL SHIFT
AND SLEW
RATE CONTROL
LOAD
Figure 1. WLCSP
ADP198
VIN
+
VIN
SEL0
SEL1
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ON EN
OFF
GND
REVERSE
POLARITY
PROTECTION
SLEW
RATE CONTROL
LEVEL SHIFT
Figure 2. LFCSP
VOUT
VOUT
LOAD
equipment. The built-in level shifter for enable logic makes the
ADP198 compatible with modern processors and general-purpose
input/output (GPIO) controllers. The LFCSP version also allows
the user to program the start-up time to control the inrush
current at turn on.
The ADP198 is available in an ultrasmall 1 mm × 1 mm, 4-ball,
0.5 mm pitch WLCSP. An 8-lead, 2 mm × 2 mm × 0.55 mm,
0.5 mm pitch LFCSP is also available.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Data Sheet
ADP198
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN to GND Pins
VOUT to GND Pins
EN to GND Pins
Continuous Drain Current
TA = 25°C
TA = 85°C
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
±1000 mA
±1000 mA
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP198 can be damaged if the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The speci-
fied values of θJA are based on a 4-layer, 4 inch × 3 inch PCB. Refer
to JESD 51-7 and JESD 51-9 for detailed information regarding
board construction. For additional information, see the AN-617
Application Note, MicroCSP™ Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) using the
formula
TJ = TB + (PD × ΨJB)
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Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
4-Ball, 0.5 mm Pitch WLCSP
8-Lead, 2 mm × 2 mm LFCSP
θJA θJC ΨJB Unit
260 4
58.4 °C/W
72.1 42.3 47.1 °C/W
ESD CAUTION
Rev. D | Page 5 of 16
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Data Sheet
THEORY OF OPERATION
ADP198
VIN
REVERSE
POLARITY
PROTECTION
VOUT
SEL0
SEL1
EN
GND
SLEW
RATE CONTROL
LEVEL SHIFT
Figure 22. Functional Block Diagram
The ADP198 is a high-side PMOS load switch that is designed
for supply operation between 1.65 V and 6.5 V. The PMOS load
switch has a low on resistance of 50 mΩ at VIN = 3.3 V and
supports 1 A of continuous load current. The ADP198 features
low quiescent current at 2.5 μA typical using a 2.8 V supply.
ADP198
The enable input incorporates a nominal 4 MΩ pull-down
resistor. SEL0 and SEL1 program the start-up time of the load
switch to reduce inrush current when the switch is turned on.
The reverse current protection circuitry prevents current from
flowing backwards through the ADP198 when the output voltage
is greater than the input voltage. A comparator senses the differ-
ence between the input and output voltages. When the difference
between the input voltage and output voltage exceeds 75 mV,
the body of the PFET is switched to VOUT and turned off or
opened. In other words, the gate is connected to VOUT.
The packaging is a space-saving 1 mm × 1 mm, 4-ball WLCSP.
The ADP198 is also available in a 2 mm × 2 mm × 0.55 mm,
0.5 mm pitch LFCSP.
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Rev. D | Page 11 of 16
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP198.PDF ] | |
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