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PDF LM3844A Data sheet ( Hoja de datos )
| Número de pieza | LM3844A | |
| Descripción | (LM3842A - LM3845A) CURRENT MODE PWM CONTROLLER | |
| Fabricantes | HTC | |
| Logotipo |  |
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CURRENT MODE PWM CONTROLLER
LM3842A/3A/4A/5A
FEATURES
8 SOP/ 8 DIP PIN Configulation
● Automatic feed forward compensation
● Optimized for offline converter
● Double pulse suppression
Compen
sation
Voltage
Feedback
1
2
8 VREF
7 Vcc
● Current mode operation to 500 KHz
● High gain totem pole output
● Internally trimmed bandgap reference
Current
Sense
3
RT/CT 4
6 OUTPUT
5 GND
● Undervoltage lockout with hysteresis
● Low start up current :＜ 0.3 mA
ORDERING INFORMATION
Device
Package
DESCRIPTION
LM3842A/3A/4A/5A D
8 SOP
LM3842A/3A/4A/5A N
8 DIP
The LM3842A is fixed frequency current-mode PWM controller. It is specially designed for Off-Line and
DC-to-DC converter applications with minimal external components.
This integrated circuit features a trimmed oscillator for precise duty cycle control, a temperature
compensated reference, high gain error amplifier, current sensing comparator, and a high current
totempole output ideally suited for driving a power MOSFET.
Protection circuitry includes built in under-voltage lockout and current limiting.
SIMPLIFIED BLOCK DIAGRAM
VREF ⑧
RT/CT ④
VFB ②
COMP ①
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Vcc
5V Undervoltage
R
Reference
Lockout
VREF
R
Undervoltage
Lockout
Oscillator
+
-
Error
Amplifie
r
Latching
PWM
ABSOLUTE MAXIMUM RATINGS (TA= 25℃)
Characteristic
Power Supply Voltage
Output Current
Analog Inputes Voltage
Error Amp Output Sink Current
Power Dissipation
Storage Temperature Range
Lead Temperature (soldering 5 sec)
Symbol
Vcc
I
VIN
ISINK
PD
Tstg
T
Value
30
±1
-0.3 to 5.5V
10
1
-65 to 150
260
⑦ Vcc
⑥ Output
⑤ Ground
③ Current
Sense
Input
Unit
V
A
V
mA
W
℃
℃
1
HTC
datasheet pdf - http://www.DataSheet4U.net/
1 page  
CURRENT MODE PWM CONTROLLER
Fig.6 Shutdown Techniques
1K
8 VREF
LM3842A/3A/4A/5A
1 COMP
330Ω
3 ISENSE
500Ω
SHUTDOWN
SHUTDOWN
TO CURRENT
SENSE-RESISTOR
Shutdown of the LM3842A can be accomplished by two methods; either raise pin 3 above 1V or
pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the
PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that
the output will remain low until the next clock cycle after the shoutdown condition at pins 1 and/or 3
is removed. In one example, an externally latched shutdown may be accomplished by adding an
SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the
reference turns off, allowing the SCR to reset.
Fig.7 Slope Compensation
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VREF 8
LM3842A
RT/CT 4
ISENSE 3
0.1μF
RT
CT
R1
R2
C
ISENSE
RSENCE
A fraction of the oscillator ramp can be resistively summed with the current sense signal to
provide slope compensation for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.
HTC
5
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