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MT6589 PDF 데이터시트 ( Data , Function )

부품번호 MT6589 기능
기능 HSPA+ Smartphone Application Processor
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MT6589 데이터시트, 핀배열, 회로
MT6589 HSPA+ Smartphone
Application Processor
Technical Brief
http://www.DataSheet4U.net/
Version:
Release date:
0.2
2012-09-26
© 2011 - 2012 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
datasheet pdf - http://www.DataSheet4U.net/
loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX




MT6589 pdf, 반도체, 판매, 대치품
MT6589
HSPA+ Smartphone Application Processor
Technical Brief
Confidential A
List of Figures
Figure 1-1: Block diagram of MT6589................................................................................................... 11
Figure 2-1 : Ball map view of MT6589 .................................................................................................. 12
Figure 2-2: Basic timing parameter for LPDDR2 commands................................................................ 32
Figure 2-3: Basic timing parameter for LPDDR2 write.......................................................................... 32
Figure 2-4: Basic timing parameter for LPDDR2 read .......................................................................... 33
Figure 2-8: Power on/off sequence with XTAL...................................................................................... 35
Figure 2-9: Power on/off sequence without XTAL................................................................................. 36
Figure 2-10: Block diagram of BBRX-ADC ........................................................................................... 38
Figure 2-11: Block diagram of 2GBBTX ................................................................................................ 41
Figure 2-12: Block diagram of APC-DAC.............................................................................................. 42
Figure 2-13: Block diagram of VBIAS-DAC .......................................................................................... 43
Figure 2-14: Block diagram of AUXADC ............................................................................................... 44
Figure 2-15: Block diagram of PLL ....................................................................................................... 47
Figure 2-16: Outlines and dimensions of FCCSP 11.8mm*11.8mm, 515-ball, 0.4mm pitch package.. 52
Figure 2-17: Top mark of MT6589......................................................................................................... 53
List of Tables
Table 2-1: Pin coordinate ...................................................................................................................... 13
Table 2-2: Acronym for pin type ............................................................................................................ 17
Table 2-3: Detailed pin description ........................................................................................................ 17
Table 2-4: Absolute maximum ratings for power supply ....................................................................... 29
Table 2-5: Recommended operating conditions for powerhttp://www.DataSheet4U.net/ supply ........................................................ 30
Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces.................................... 33
Table 2-8: Mode selection of chip (PMU 6320 pin) ............................................................................... 34
Table 2-9: Constant tied pins of MT6589 .............................................................................................. 34
Table 2-10: Baseband downlink specifications ..................................................................................... 38
Table 2-11: Baseband uplink transmitter specifications ........................................................................ 40
Table 2-12: Baseband uplink transmitter specifications ........................................................................ 41
Table 2-13: APC-DAC specifications..................................................................................................... 42
Table 2-14: VBIAS-DAC specifications ................................................................................................. 43
Table 2-15: Definitions of AUXADC channels ....................................................................................... 44
Table 2-16: AUXADC specifications ...................................................................................................... 45
Table 2-17: Clock squarer 1 & 2 specifications ..................................................................................... 46
Table 2-18: ARMPLL specifications....................................................................................................... 47
Table 2-19: MAINPLL specifications ..................................................................................................... 48
Table 2-20: MMPLL specifications ........................................................................................................ 48
Table 2-21: ISPPLL specifications......................................................................................................... 48
Table 2-22: UNIVPLL specifications...................................................................................................... 49
Table 2-23: MSDCPLL specifications.................................................................................................... 49
Table 2-24: TVDPLL specifications ....................................................................................................... 49
Table 2-25: LVDSPLL specifications ..................................................................................................... 50
Table 2-26: MDPLL1 & MDPLL2 specifications .................................................................................... 50
Table 2-27: WPLL specifications ........................................................................................................... 50
Table 2-28: WHPLL specifications ........................................................................................................ 50
Table 2-29: MCUPLL1 & MCUPLL2 specifications ............................................................................... 51
Table 2-30: Temperature sensor specifications..................................................................................... 51
Table 2-31: Thermal operating specifications ....................................................................................... 52
MediaTek Confidential
© 2012 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6589 전자부품, 판매, 대치품
MT6589
HSPA+ Smartphone Application Processor
Technical Brief
Confidential A
1.1 Platform Features
General
Smartphone two MCU subsystems
architecture
SLC NAND flash and eMMC bootloader
AP MCU subsystem
Quad-core ARM® Cortex-A7 MPCoreTM
operating at 1.2GHz
NEON multimedia processing engine
with SIMDv2/VFPv4 ISA support
32KB L1 I-cache and 32KB L1 D-cache
1MB unified L2 cache
DVFS technology with adaptive
operating voltage from 0.95V to 1.26V
MD MCU subsystem
ARM® Cortex-R4 processor with
maximum 480MHz operation frequency
64KB I-cache, 32KB D-cache
256KB TCM (tightly-coupled memory)
DSP for running modem/voice tasks,
with maximum 240MHz operation
frequency
High-performance AXI and AHB bus
General DMA engine and dedicated
DMA channels for peripheral data
transfer
Watchdog timer for system error
recovery
Power management for clock gating
control
MD external interfaces
Supports dual SIM/USIM interface
Interface pins with RF and radio-related
peripherals (antenna tuner, PA, …)
UART for modem logging/debugging
purpose
External memory interface
Supports LPDDR2 up to 2GB
32-bit data bus width
Memory clock up to 533MHz
Supports self-refresh/partial self-refresh
mode
Low-power operation
Programmable slew rate for memory
controller’s IO pads
Supports dual rank memory device
Advanced bandwidth arbitration control
Security
ARM® TrustZone® Security
Connectivity
USB2.0 high-speed OTG supporting 15
Tx and 15 Rx endpoints
USB2.0 full-speed host
NAND flash controller supporting NAND
http://www.DataSheet4U.net/
bootable, iNAND2® and MoviNAND®
4 UART for GPS, BT, FM-RDS, modem
and debugging interfaces
IrDA FIR/MIR/SIR
SPI for external device
7 I2C to control peripheral devices, e.g.
CMOS image sensor, LCM or FM
receiver module
I2S for connection with optional external
hi-end audio codec
GPIOs
4 sets of memory card controllers
supporting SD/SDHC/MS/MSPRO/MMC
and SDIO2.0/3.0 protocols
Operating conditions
Core voltage: 1.05V
Processor DVFS voltage: 0.95V ~ 1.26V
(Typ. 1.05V; sleep mode 0.85V)
Processor SRAM voltage: 1.05V ~
1.26V (Typ. 1.05V; sleep mode 0.85V)
MediaTek Confidential
© 2012 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 7 of 53
datasheet pdf - http://www.DataSheet4U.net/
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