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PDF TK3715 Data sheet ( Hoja de datos )
| Número de pieza | TK3715 | |
| Descripción | SoC Bridge | |
| Fabricantes | Teknovus | |
| Logotipo |  |
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TK3715 Data Sheet
Turbo-EPONTM SoC Bridge for China Standard ONU
FEATURES
• 2.5/1.25Gbps downstream with auto-
detection, 1.25Gbps upstream
• Ultra low jitter Integrated EPON SerDes
(2.5/1.25Gbps)
• IEEE 802.3ah EPON MAC
• Triple Churning Key decryption
• China EPON standard OAM control
• 802.3ah OAM control
• Independent 10/100 and 10/100/1000
Subscriber Ports
• 802.3 10/100 MAC and 10/100/1000 MAC
• MAC Address Learning for up to 64 MAC
Addresses per Ethernet port for 802.1D
Bridging
• Highly flexible 802.1Q VLAN support
• 802.1p/q support
• 40 fully-configurable queues
• 1.5 MB of integrated packet buffering
• Line-rate layer 2/3/4 packet classification
and filtering for up to 256 entries
• Per-port 802.3x flow control
• 802.3ah Forward Error Correction (FEC)
• Up to eight Logical Link IDs (LLID)
• Internal Management Information Base
(MIB) counters for network statistics
• Remote Monitoring (RMON) statistics
• Embedded 80C51 processor with
integrated memory
• IEEE 1149.1 JTAG Boundary Scan
• Low Power 3.3V I/O and 1.2V Core supply
• 128-pin LQFP with exposed pad, and
TFBGA-169 packages
• Pin compatibility with TK3713 and TK3714
• Industrial temperature operation, -40°C to
+85°C
DESCRIPTION
The TK3715 chip for Optical Network Units (ONU) is an IEEE 802.3ah-compliant System-on-Chip (SoC) Ethernet
http://www.DataSheet4U.com/
Passive Optical Network (EPON) Bridge. The TK3715 supports all the functions needed to comply with the China
standard for EPON. It provides high-speed, fiber optic broadband access for residential and business CPE
(Customer Premises Equipment) ONUs. The auto-sensing Turbo-EPONTM mode operates at 1.25GHz
downstream with legacy systems and 2.5GHz downstream with Turbo-EPON OLTs, such as the TK3723. The
TK3715 is compatible with all Teknovus OLT chipsets. The TK3715 is cost-optimized for markets using the China
standard for EPON. The high level of integration in the TK3715 greatly simplifies ONU design. The TK3715
contains an 802.3ah EPON MAC, a SerDes, line-rate L2/L3/L4 classification and filtering, China EPON
decryption, Forward Error Correction (FEC), integrated packet buffering, two independent subscriber ports and an
embedded processor. The processor supports a sophisticated ONU management system, including alarms,
provisioning, DHCP and IGMP functions for a stand-alone IPTV solution at the ONU. Glueless interfaces are
provided for an external EPON transceiver, FLASH and 10/100/1000 PHYs.
The TK3715 can be managed from the OLT over the EPON using 802.3ah standard OAM messaging and China
OAM extensions.
Combined with the hardware-based DBA of the Teknovus OLT chipset and the Teknovus Host Interface
Software, the TK3715 is ideal for ONUs designed for IPTV. This complete EPON system solution provides all the
necessary low-level management software, allowing developers to get new products to market quickly.
The TK3715 is offered in low-cost 128-pin Low-profile Quad Flat Pack (LQFP) and 169-ball Thin and Fine Pitch
Ball Grid Array (TFBGA) packages. The TFBGA package with its 11x11mm body size is ideally suited for SFP
applications.
Rev 1.00
Confidential - View Under NDA Only
1 page  
TK3715 Data Sheet
Turbo-EPONTM SoC Bridge for China Standard ONU
4.2 TFBGA-169 Package .......................................................................................................................................... 55
5 TK3715 Ordering Information ...................................................................................................................................... 57
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Revision History ................................................................................................................................................. 6
Local-Side 10/100/1000 MII/GMII/TBI Interface (Port 1) .................................................................................. 12
Local-Side 10/100 MII Interface (Port 2) .......................................................................................................... 14
MDIO Interface................................................................................................................................................. 14
Ethernet PON Transceiver Serial Interface ...................................................................................................... 15
UART Interface ................................................................................................................................................ 15
Reference Clocks and Global Reset ................................................................................................................ 15
JTAG Interface................................................................................................................................................. 16
GPIO Interface ................................................................................................................................................. 16
Processor Bus Interface................................................................................................................................... 17
Test and Configuration Interface ...................................................................................................................... 17
Digital Power and Ground ................................................................................................................................ 17
Internal SerDes Power ..................................................................................................................................... 18
IPv6 Next Header............................................................................................................................................. 23
JTAG Instructions and Operations ................................................................................................................... 34
Absolute Maximum Ratings ............................................................................................................................. 36
Recommended Operating Conditions .............................................................................................................. 37
DC Characteristics ........................................................................................................................................... 38
System and SerDes Reference Clocks Timing ....http.://ww.w.Dat.aShe.et4U.c.om/....................................................................................... 39
Local-Side MII Input Timing of the 10/100 Ethernet Port.................................................................................. 40
Local-Side MII Output Timing of the 10/100 Ethernet Port............................................................................... 41
Local-Side MII/GMII Input Timing of the 10/100/1000 Ethernet Port ................................................................ 42
Local-Side MII/GMII Output Timing of the 10/100/1000 Ethernet Port ............................................................. 43
Local-Side TBI Input Timing............................................................................................................................. 44
Local-Side GMII Input Timing........................................................................................................................... 44
Local-Side TBI/GMII Output Timing ................................................................................................................. 45
Ethernet Serial Management Timing................................................................................................................ 46
SerDes Output Timing...................................................................................................................................... 47
SerDes Input Timing ........................................................................................................................................ 47
SPI Timing ....................................................................................................................................................... 48
Reset and CLK_25 Timing ............................................................................................................................... 49
LQFP-128 Package Dimensions ...................................................................................................................... 51
TFBGA-169 Package Dimensions ................................................................................................................... 56
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block Diagram of TK3715-Based ONU .............................................................................................................. 5
TK3715 Pin Diagram in 128-LQFP Package.................................................................................................... 10
TK3715 Ball Array in TFBGA-169 Package ..................................................................................................... 11
TK3715 Block Diagram .................................................................................................................................... 19
MII Interface with 10/100 Ethernet PHY ........................................................................................................... 20
Page 5 of 58
Confidential - View Under NDA Only
Rev 1.00
5 Page 
TK3715 Data Sheet
Turbo-EPONTM SoC Bridge for China Standard ONU
LQFP TFBGA
Pin Ball
Signal Name
I/O
Signal Description
101 L4 GMII_TXEN/
TBI_TXD8
100 N2 GMII_TXER/
TBI_TXD9
O This is a dual function pin:
• MII/GMII: Transmit Data Enable to PHY
• TBI: Transmit Data [8] to SerDes
O This is a dual function pin:
• MII/GMII: Transmit Data Error to PHY
• TBI: Transmit Data [9] to SerDes
* When not used, pull down unused clock inputs with the 1K-4.7Kohm resistors, and leave all other pins unconnected.
Table 3. Local-Side 10/100 MII Interface (Port 2)
LQFP
Pin
28
TFBGA
Ball
E12
Signal Name
MII_RXCLK
30 D11 MII_RXD0
31 D12 MII_RXD1
32 C13 MII_RXD2
33 C12 MII_RXD3
27 E13 MII_RXDV
25 E11 MII_RXER
21 G11 MII_CRS
22 F13 MII_COL
24 F11 MII_TXCLK
16 H13 MII_TXD0
17 H11 MII_TXD1
19 G12 MII_TXD2
20 F12 MII_TXD3
14 H12 MII_TXEN
13 J13 MII_TXER
I/O Signal Description
I* Receive Clock. Generated by PHY to clock-in MII_RXD[3:0], MII_RXER, and
MII_RXDV
I Receive data [0] from 10/100 PHY to TK3715
I Receive data [1] from 10/100 PHY to TK3715
I Receive data [2] from 10/100 PHY to TK3715
I Receive data [3] from 10/100 PHY to TK3715
I Receive Data Valid. Signals the presence of data on MII_RXD[3:0]
I Receive Error. Indicateshttp://www.DataSheet4U.com/ a transmit coding error has occurred
I Carrier Sense. Indicates when the line is busy
I Collision. In half-duplex mode, indicates a collision
I* Transmit Clock. Generated by PHY to clock-out MII_TXD[3:0], MII_TXER, and
MII_TXEN
O Transmit data [0] from TK3715 to PHY
O Transmit data [1] from TK3715 to PHY
O Transmit data [2] from TK3715 to PHY
O Transmit data [3] from TK3715 to PHY
O Transmit Data Enable. Signals the presence of data on MII_TXD[3:0]
O Transmit Data Error
* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other pins unconnected (NC).
Table 4.
LQFP
Pin
10
11
MDIO Interface
TFBGA
Ball
K13
J12
Signal Name
MDIO_DATA
MDIO_CLK
I/O Signal Description
I/O Management Data I/O. Serial Access for configuration of external PHY(s)
O Management Data Clock. Clock for R/W of device configuration register
Page 11 of 58
Confidential - View Under NDA Only
Rev 1.00
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TK3715.PDF ] | |
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