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ADP5050 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP5050은 전자 산업 및 응용 분야에서
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부품번호 ADP5050 기능
기능 5-Channel Integrated Power Solution
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ADP5050 데이터시트, 핀배열, 회로
Data Sheet
5-Channel Integrated Power Solution with Quad
Buck Regulators and 200 mA LDO Regulator
ADP5050
FEATURES
Wide input voltage range: 4.5 V to 15 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse or I2C interface
I2C interface with interrupt on fault conditions
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Channel 5: 200 mA low dropout (LDO) regulator
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Dynamic voltage scaling (DVS) for Channel 1 and Channel 4
Precision enable with 0.8 V accurate threshold
Active output discharge switch
Programmable phase shift in 90° steps
Individual channel FPWM/PSM mode selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
Low input voltage detection
Overheat detection on junction temperature
UVLO, OCP, and TSD protection
48-lead, 7 mm × 7 mm LFCSP package
−40°C to +125°C junction temperature
APPLICATIONS
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5050 combines four high performance buck regulators
and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP
package that meets demanding performance and board space
requirements. The device enables direct connection to high input
voltages up to 15 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Combining Channel 1 and Channel 2 in a parallel configuration
can provide a single output with up to 8 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver output current of 1.2 A.
TYPICAL APPLICATION CIRCUIT
C1
4.5V TO 15V
VREG
VDD
C0
PVIN1
C2
COMP1
EN1
SS12
ADP5050
INT VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1
C3
DL1 Q1
PGND RILIM1
DL2 RILIM2
PVIN2
C5
COMP2
EN2
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
VREG
SW2
Q2
BST2
FB2
C6
L1
L2
VOUT1
C4
VOUT2
C7
PVIN3
C8
COMP3
EN3
SS34
http://www.DataSheet4U.com/
PVIN4
C11
COMP4
EN4
1.7V TO 5.5V PVIN5
C14 EN5
VDDIO
SCL
SDA
CHANNEL 3
BUCK REGULATOR
(1.2A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
CHANNEL 5
200mA LDO
REGULATOR
I2C ALERT
BST3
SW3
C9
FB3
PGND3
BST4
SW4
FB4
C12
PGND4
VOUT5
FB5
PWRGD
nINT
L3 VOUT3
C10
L4 VOUT4
C13
VOUT5
C15
EXPOSED PAD
Figure 1.
The switching frequency of the ADP5050 can be programmed
or synchronized to an external clock. The ADP5050 contains a
precision enable pin on each channel for easy power-up sequencing
or adjustable UVLO threshold.
The ADP5050 integrates a general-purpose LDO regulator with
low quiescent current and low dropout voltage that provides up
to 200 mA of output current.
The optional I2C interface provides the user with flexible
configuration options, including adjustable and fixed output
voltage options, junction temperature overheat warning, low
input voltage detection, and dynamic voltage scaling (DVS).
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5050 pdf, 반도체, 판매, 대치품
ADP5050
DETAILED FUNCTIONAL BLOCK DIAGRAM
EN1
COMP1
FB1
EN2
COMP2
FB2
RT
SYNC/MODE
SS12
SS34
PWRGD
CHANNEL 1 BUCK REGULATOR
0.8V –
+
1MΩ
CLK1
+
OCP –
HICCUP
AND
LATCH-OFF
SLOPE
COMP
0.8V +
EA1
VID1
+
+
CMP1
CLK1
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
FREQUENCY
FOLDBACK
OVP
+ LATCH-OFF
0.99V
0.72V PWRGD1
UVLO1
+
ACS1
VREG
Q1
DRIVER
QDG1
VREG
DRIVER
ZERO
CROSS
CURRENT-LIMIT
SELECTION
CHANNEL 2 BUCK REGULATOR
CURRENT BALANCE
DUPLICATE CHANNEL 1
OSCILLATOR
SOFT START
DECODER
QPWRGD
HOUSEKEEPING
LOGIC
http://www.DataSheet4U.com/
PVIN1
VREG
INTERNAL
REGULATOR
POWER-ON
I2C
RESET INTERFACE
AND
REGISTERS
PVIN1
BST1
SW1
DL1
PGND
PVIN2
BST2
DL2
SW2
VREG
VDD
VDDIO
SCL
SDA
nINT
EN3
COMP3
FB3
EN4
COMP4
FB4
PVIN5
EN5
CHANNEL 3 BUCK REGULATOR
0.8V –
+
1MΩ
CLK3
+
OCP –
HICCUP
AND
LATCH-OFF
SLOPE
COMP
0.8V +
EA3
VID3
+
+
CMP3
CLK3
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
FREQUENCY
FOLDBACK
OVP
+ LATCH-OFF
0.99V
0.72V PWRGD3
UVLO3
+
ACS3
VREG
DRIVER
VREG
DRIVER
ZERO
CROSS
QDG3
Q3
Q4
CHANNEL 4 BUCK REGULATOR
DUPLICATE CHANNEL 3
CHANNEL 5 LDO REGULATOR
0.8V –
+
1MΩ
LDO
CONTROL
Q7
Figure 2.
Rev. 0 | Page 4 of 60
EA5
+
0.5V
PVIN3
BST3
SW3
PGND3
PVIN4
BST4
SW4
PGND4
VOUT5
FB5
Data Sheet

4페이지










ADP5050 전자부품, 판매, 대치품
Data Sheet
Parameter
CHANNEL 2 SYNC BUCK REGULATOR
FB2 Pin
Fixed Output Options
Adjustable Feedback Voltage
Feedback Voltage Accuracy
Symbol
VOUT2
VFB2
VFB2(DEFAULT)
Feedback Bias Current
SW2 Pin
High-Side Power FET
On Resistance
Current-Limit Threshold
IFB2
RDSON(2H)
ITH(ILIM2)
Minimum On Time
Minimum Off Time
Low-Side Driver, DL2 Pin
Rising Time
Falling Time
Sourcing Resistor
Sinking Resistor
Error Amplifier (EA), COMP2 Pin
EA Transconductance
Soft Start
Soft Start Time
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
CHANNEL 3 SYNC BUCK REGULATOR
FB3 Pin
Fixed Output Options
tMIN_ON2
tMIN_OFF2
tRISING2
tFALLING2
tSOURCING2
tSINKING2
gm2
tSS2
tHICCUP2
RDIS2
VOUT3
Adjustable Feedback Voltage
Feedback Voltage Accuracy
VFB3
VFB3(DEFAULT)
Feedback Bias Current
SW3 Pin
High-Side Power FET
On Resistance
Low-Side Power FET
On Resistance
Current-Limit Threshold
Minimum On Time
Minimum Off Time
Error Amplifier (EA), COMP3 Pin
EA Transconductance
Soft Start
Soft Start Time
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
IFB3
RDSON(3H)
RDSON(3L)
ITH(ILIM3)
tMIN_ON3
tMIN_OFF3
gm3
tSS3
tHICCUP3
RDIS3
Min
3.3
−0.55
−1.25
−1.5
3.50
1.91
4.95
310
2.0
1.20
−0.55
−1.25
−1.5
1.7
310
2.0
Typ Max
0.800
5.0
+0.55
+1.0
+1.5
0.1
110
4.4
2.63
6.44
117
1/9 × tSW
5.28
3.08
7.48
155
20
3.4
10
0.95
470 620
2.0
http://www.DataSheet4U.com/
7 × tSS2
250
8.0
0.800
1.80
+0.55
+1.0
+1.5
0.1
225
150
2.2
90
1/9 × tSW
2.55
120
470 620
2.0
7 × tSS3
250
8.0
Rev. 0 | Page 7 of 60
ADP5050
Unit Test Conditions/Comments
V Fuse trim or I2C interface
(3-bit value)
V
% TJ = 25°C
% 0°C ≤ TJ ≤ 85°C
% −40°C ≤ TJ ≤ +125°C
µA Adjustable voltage
mΩ Pin-to-pin measurement
A RILIM2 = floating
A RILIM2 = 47 kΩ
A RILIM2 = 22 kΩ
ns fSW = 250 kHz to 1.4 MHz
ns fSW = 250 kHz to 1.4 MHz
ns CISS = 1.2 nF
ns CISS = 1.2 nF
µS
ms SS12 connected to VREG
ms
ms
V Fuse trim or I2C interface
(3-bit value)
V
% TJ = 25°C
% 0°C ≤ TJ ≤ 85°C
% −40°C ≤ TJ ≤ +125°C
µA Adjustable voltage
mΩ Pin-to-pin measurement
mΩ Pin-to-pin measurement
A
ns fSW = 250 kHz to 1.4 MHz
ns fSW = 250 kHz to 1.4 MHz
µS
ms SS34 connected to VREG
ms
ms

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