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ADP5061 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP5061은 전자 산업 및 응용 분야에서
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부품번호 ADP5061 기능
기능 Tiny I2C Programmable Linear Battery Charger
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ADP5061 데이터시트, 핀배열, 회로
Data Sheet
Tiny I2C Programmable Linear Battery Charger
with Power Path and USB Mode Compatibility
ADP5061
FEATURES
2.6 mm × 2 mm WLCSP package
Fully programmable via I2C
Flexible digital control inputs
Up to 2.1 A current from an ac charger in LDO mode
Operating input voltage from 4.0 V to 6.7 V
Tolerant input voltage from −0.5 V to +20 V (USB VBUS)
Fully compatible with USB 3.0 and USB Battery Charging
Specification 1.2
Built-in current sensing and limiting
As low as 30 mΩ battery isolation FET between battery and
charger output
Thermal regulation prevents over heating
Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging
temperature specifications
SYS_EN flag permits the system to be disabled until battery is at
minimum required level for guaranteed system start-up
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDAs, audio, and GPS devices
Portable medical devices
Mobile phones
GENERAL DESCRIPTION
The ADP5061 charger is fully compliant with USB 3.0 and the
USB Battery Charging Specification 1.2 and enables charging
via the mini USB VBUS pin from a wall charger, car charger, or
USB host port.
The ADP5061 operates from a 4 V to 6.7 V input voltage range
but is tolerant of voltages up to 20 V. The 20 V voltage tolerance
alleviates the concerns about the USB bus spiking during dis-
connect or connect scenarios.
The ADP5061 features an internal FET between the linear
charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
TYPICAL APPLICATION CIRCUIT
AC OR
USB
VBUS
C1
10µF
VIN
CBP
C2
10nF
ADP5061
ISO_S
SYSTEM
C3
47µF
SCL
SDA
DIG_IO1
DIG_IO2
DIG_IO3
SYS_EN
CHARGER
CONTROL
BLOCK
AGND
Figure 1.
ISO_B
BAT_SNS
+ Li-ion
THR
C4
22µF
ILED
VLED
http://www.DataSheet4U.com/
scenario, which allows for immediate system function on connec-
tion to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5061 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5061 has three factory programmable digital input/output
pins that provide maximum flexibility for different systems.
These digital input/output pins permit combinations of features
such as, input current limits, charging enable and disable,
charging current limits, and a dedicated interrupt output pin.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.




ADP5061 pdf, 반도체, 판매, 대치품
ADP5061
Data Sheet
Parameter
LDO AND HIGH VOLTAGE BLOCKING
Regulated System Voltage
Load Regulation
High Voltage Blocking FET (LDO FET)
On Resistance
Maximum Output Current
VINx Input Voltage, Good Threshold
Rising
VINx Falling
VINx Input Overvoltage Threshold
Hysteresis
VINx Transition Timing
THERMAL CONTROL
Isothermal Charging Temperature
Thermal Early Warning Temperature
Thermal Shutdown Temperature
THERMISTOR CONTROL
Thermistor Current
10,000 NTC
100,000 NTC
Thermistor Capacitance
Cold Temperature Threshold
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
Hot Temperature Threshold
Resistance Thresholds
Hot to Typical Resistance
Typical to Hot Resistance
JEITA1 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS5
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Typical Temperature
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
JEITA Warm Temperature
Resistance Thresholds
Hot to Warm Resistance
Warm to Hot Resistance
JEITA Hot Temperature
Symbol Min Typ
Max Unit Test Conditions/Comments
VISO_STRK
4.214
RDS(ON)HV
VVIN_OK_RISE 3.75
VVIN_OK_FALL
VVIN_OV
ΔVVIN_OV
TVIN_RISE
TVIN_FALL
6.7
10
10
4.3
−0.28
330
2.1
3.9
3.6
6.9
0.1
4.386
485
4.0
3.7
7.2
V VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_S = 100 mA,
LDO mode2
%/A IISO_S = 0 m A to 1500 mA
mΩ IVIN = 500 mA
A VISO_S = 4.3 V, LDO mode
V
V
V
V
µs Minimum rise time for VINx from 5 V to 20 V
µs Minimum fall time for VINx from 4 V to 0 V
TLIM 115 °C
TSDL 130 °C
TSD 140 °C TJ rising
110 °C TJ falling
INTC_10k
INTC_100k
CNTC
TNTC_COLD
400 μA
40 μA
100 pF
0 °C
RCOLD_FALL
RCOLD_RISE
TNTC_HOT
20,500
25,600
24,400
60
30,720
http://www.DataSheet4U.com/
°C
RHOT_FALL
RHOT_RISE
2750
3700
3350
3950
No battery charging occurs
No battery charging occurs
TJEITA_COLD
0
°C
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
20,500
25,600
24,400
10
30,720
°C
RTYP_FALL
RTYP_RISE
TJEITA_TYP
13,200 16,500
15,900
19,800
°C
RWARM_FALL
RWARM_RISE
TJEITA_WARM
4260
RHOT_FALL
RHOT_RISE
TJEITA_HOT
2750
5800
5200
45
3700
3350
60
6140
3950
°C
°C
No battery charging occurs
Battery charging occurs at 50% of programmed level
Normal battery charging occurs at default/programmed
levels
Battery termination voltage (VTRM) is reduced by 100 mV
No battery charging occurs
Rev. 0 | Page 4 of 44

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ADP5061 전자부품, 판매, 대치품
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4. Absolute Maximum Ratings
Parameter
VIN1, VIN2, VIN3 to AGND
All Other Pins to AGND
Continuous Drain Current, Battery Supple-
mentary Mode, from ISO_Bx to ISO_Sx
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.5 V to +20 V
–0.3 V to +6 V
2.1 A
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADP5061
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for surface-
mount packages.
Table 5. Thermal Resistance
Package Type
θJA θJC θJB Unit
20-Lead WLCSP1
46.8 0.7 9.2 °C/W
1 5 × 4 array, 0.5 mm pitch (2.6 mm × 2.0 mm); based on a JEDEC 2S2P, 4-layer
board with 0 m/sec airflow.
Maximum Power Dissipation
The maximum safe power dissipation in the ADP5061 package
is limited by the associated rise in junction temperature (TJ) on
the die. At a die temperature of approximately 150°C (the glass
transition temperature), the properties of the plastic change.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, thereby perma-
nently shifting the parametric performance of the ADP5061.
Exceeding a junction temperature of 175°C for an extended
period can result in changes in the silicon devices, potentially
causing failure.
ESD CAUTION
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Rev. 0 | Page 7 of 44

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