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PDF 5764A Data sheet ( Hoja de datos )
| Número de pieza | 5764A | |
| Descripción | AD5764 | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Complete, Quad, 16-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DAC
AD5764
FEATURES
Complete quad 16-bit D/A converter
Programmable output range: ±10 V, ±10.25 V, or ±10.5 V
±1 LSB max INL error, ±1 LSB max DNL error
Low noise : 60 nV/√Hz
Settling time: 10µs max
Integrated reference buffers
Internal reference, 10 ppm/°C
On-chip temp sensor, ±5°C accuracy
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjust
Logic output control pins
DSP/microcontroller compatible serial interface
Temperature range:−40°C to +85°C
iCMOS™ Process Technology
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Data acquisition systems
Automatic Test Equipment
Automotive test and measurement
High accuracy instrumentation
GENERAL DESCRIPTION
The AD5764 is a quad, 16-bit serial input, voltage output
digital-to analog converter that operates from supply voltages of
±12 V up to ±15 V. Nominal full-scale output range is ±10 V,
provided are integrated output amplifiers, reference buffers,
internal reference, and proprietary power-up/power-down
control circuitry. It also features a digital I/O port that may be
programmed via the serial interface, and an analog temperature
sensor. The part incorporates digital offset and gain adjust
registers per channel.
The AD5764 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise and 10 µs settling time and includes an on-chip 5 V
reference with a reference tempco of 10 ppm/°C max. During
power-up (when the supply voltages are changing), Vout is
clamped to 0V via a low impedance path.
The AD5764 uses a serial interface that operates at clock rates up
to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or straight binary formats. The asynchronous
clear function clears all DAC registers to either bipolar zero or
zero-scale depending on the coding used. The AD5764 is ideal for
both closed-loop servo control and open-loop control
applications. The AD5764 is available in a 32-lead TQFP package,
and offers guaranteed specifications over the −40°C to +85°C
industrial temperature range. See functional block diagram,
Figure 1.
iCMOS™ Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC performance.
Rev. PrC
21-Oct-04
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
Preliminary Technical Data
Parameter
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (D0,D1, SDO) 2
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage
Current
High Impedance Output
Capacitance
TEMP SENSOR
Accuracy
Output Voltage @ 25°C
Output Voltage Scale Factor
Output Voltage Range
Output Load Current
Power On Time
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity4
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
A Grade1 B Grade1 C Grade1 Unit
2 2 2 V min
0.8 0.8 0.8 V max
±10 ±10 ±10 µA max
10 10 10 pF max
0.4
DVCC – 1
0.4
DVCC – 0.5
±1
5
0.4
DVCC – 1
0.4
DVCC – 0.5
±1
5
0.4
DVCC – 1
0.4
DVCC – 0.5
±1
5
V max
V min
V max
V min
µA max
pF typ
±1
±5
1.5
5
0/3.0
200
10
±1
±5
1.5
5
0/3.0
200
10
±1
±5
1.5
5
0/3.0
200
10
°C typ
°C max
V typ
mV/°C typ
V min/max
µA max
ms typ
11.4/15.75 11.4/15.75 11.4/15.75 V min/max
2.7/5.5
2.7/5.5
2.7/5.5
V min/max
−85 −85 −85 dB typ
3.75 3.75 3.75 mA/Channel max
2.75 2.75 2.75 mA/Channel max
1 1 1 mA max
244 244 244 mW typ
AD5764
Test Conditions/Comments
DVCC = 2.7 V to 5.5 V, JEDEC
compliant
Total for All Pins. TA = TMIN to TMAX.
DVCC= 5 V ± 10%, sinking 200 µA
DVCC = 5 V ± 10%, Sourcing 200
µA
DVCC = 2.7 V to 3.6 V, Sinking 200
µA
DVCC = 2.7 V to 3.6 V, Sourcing
200 µA
SDO only
SDO only
At 25°C
−40°C < T <+85°C
Current source only.
To within ±5°C
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND. TBD mA
typ
±12 V operation output
unloaded
4 Guaranteed by characterization. Not production tested.
Rev. PrC 21-Oct-04| Page 5 of 28
5 Page 
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5764
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
32
1
8
9
PIN 1
INDICATOR
AD5764
TOP VIEW
(Not to Scale)
25
24
17
16
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
Figure 6. 32-Lead TQFP Pin Configuration Diagram
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1 SYNC
2 SCLK13
3 SDIN13
4 SDO
5 CLR13
6 LDAC
7, 8
9
10
11
12
13, 31
14
15, 30
16
17
D0, D1
RSTOUT
RSTIN
DGND
DVCC
AVDD
PGND
AVSS
ISCC
AGNDD
Function
Active Low Input. This is the frame synchronization signal for the serial interface.
While SYNC is low, data is transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.
This operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or
readback mode.
Active Low Input. Asserting this pin sets the DAC registers to 0x0000.
Load DAC. Logic input. This is used to update the DAC registers and consequently
the analog output. When tied permanently low, the addressed DAC register is
updated on the 24th clock of the serial register write. If LDAC is held high during the
write cycle, the DAC input register is updated but the output is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
D0 and D1 form a digital I/O port. The user can configure these pins as inputs or
outputs that are configurable and readable over the serial interface. When
configured as inputs, these pins have weak internal pull-ups to DVCC.
Reset Logic Output. This is the output from the on-chip voltage monitor used in the
reset circuit. If desired, it may be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic.
Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation,
RSTIN should be tied to Logic 1.
Digital GND Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as
outputs, D0 and D1 are referenced to DVCC.
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 15.75 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –15.75 V.
This pin us used in association with an external resistor to AGND to program the
short-circuit current of the output amplifiers.
Ground Reference Pin for DAC D Output amplifier.
13 Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
Rev. PrC 21-Oct-04| Page 11 of 28
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet 5764A.PDF ] | |
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