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PDF AR8031 Data sheet ( Hoja de datos )
| Número de pieza | AR8031 | |
| Descripción | Integrated 10/100/1000 Mbps Ethernet Transceiver | |
| Fabricantes | Atheros Communications | |
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Data Sheet
August 2011
Version 1.1
AR8031 Integrated 10/100/1000 Mbps Ethernet
Transceiver
General Description
The AR8031 is part of the Arctic family of
devices — which includes the AR8031, AR8033,
and AR8035. The AR8031 is Atheros’ 4th
generation, single port, 10/100/1000 Mbps, Tri-
speed Ethernet PHY. It supports both RGMII
and SGMII interfaces to the MAC.
The AR8031 provides a low power, low BOM
(Bill of Materials) cost solution for
comprehensive applications including
enterprise, carrier and home networks such as
CPE, home gateway, enterprise switch, carrier
switch/router, mobile base station and base
station controller, optical module and media
converter, industry automation and
measurement.
The AR8031 integrates Atheros Green ETHOS®
power saving technologies and significantly
saves power not only during the work time,
but also overtime. Atheros Green ETHOS®
power savings include ultra-low power in
cable unplugged mode or port power down
mode, and automatic optimized power saving
based on cable length. The AR8031 also
supports IEEE 802.3az EEE standard (Energy
Efficient Ethernet) and Atheros proprietary
SmartEEE. SmartEEE allows legacy MAC/SoC
devices without 802.3az support to function as
a complete 802.3az system. Further, the AR8031
supports Wake-on-LAN (WoL) feature to be
able to help manage and regulate total system
power requirements.
The AR8031 embeds CDT (Cable Diagnostics
Test) technology on-chip which allows
customers to measure cable length, detect the
cable status, and identify remote and local PHY
malfunctions, bad or marginal patch cord
segments or connectors. Some of the possible
problems that can be detected include opens,
shorts, cable impedance mismatch, bad
connectors, termination mismatch, and a bad
transformer.
The AR8031 requires only a single, 3.3V power
supply. On-chip regulators provide all the
other required voltages. It integrates the
termination R/C circuitry on both the MAC
interfaces (RGMII/SGMII) and the serial
resistors for the line side.
The AR8031 device also incorporates a 1.25
GHz SerDes. This interface can be connected
directly to a fiber-optic transceiver for 1000
BASE-X /100 BASE-FX mode or to MAC
device for SGMII interface.
The AR8031 supports both 1588v2 and
synchronous Ethernet to offer a complete time
synchronization solution to meet the next
generation network requirements. The key new
features supported by the device are:
n Clock synchronization between slave and
grandmaster by the exchange of PTP
packets. Supports IEEE 1588v2 by offering a
1588 paket parser, accurate time-stamping
and insertion to support both one-step and
two-step clock modes
n Supports both IEEE 1588v2 and
Synchronous Ethernet by offering recovered
clock output from data on the network-line
side.
The AR8031 supports IEEE 802.3az Energy
Efficient Ethernet (EEE) standard. The key
features supported by the device are:
n 10 BASE-Te PHY uses reduced transmit
amplitude.
n 100 BASE-TX and 1000 BASE-T use Low
Power Idle (LPI) mode to turn off unused
analog and digital blocks to save power
while data traffic is idle.
Features
n 10/100/1000 BASE-T IEEE 802.3 compliant
n Supports 1000 BASE-T PCS and auto-
negotiation with next page support
n Supports RGMII and/or SGMII interfaces
to MAC devices
n Supports Fiber and Copper combo mode
when MAC interface works in RGMII mode
n Supports additional IEEE 1000 BASE-X and
100 BASE-FX with Integrated SerDes
n RGMII timing modes support internal delay
and external delay on Rx path
© 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,
Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The
Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.datasheet4u.com/
1 page  
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR8031 Functional Block Diagram .............. 2
Revision History ............................................. 3
Table of Contents ............................................ 5
1 Pin Descriptions ............................ 9
1.1 Power-on Strapping Pins ...................... 13
1.1.1 Mode Definition .......................... 14
2 Functional Description ............... 15
2.2 Modes of Operation ............................... 16
2.2.1 Operation Mode, Copper .......... 16
2.2.2 Operation Mode, Fiber ............... 16
2.2.3 Operation Mode, Media Converter
17
2.2.4 Operation Mode, Auto-Media
Detect (Combo) ........................... 17
2.3 Transmit Functions ................................ 18
2.4 Receive Functions .................................. 18
2.4.1 Decoder Modes ........................... 18
2.4.2 Analog to Digital Converter ...... 18
2.4.3 Echo Canceller ............................. 18
2.4.4 NEXT Canceller .......................... 18
2.4.5 Baseline Wander Canceller ....... 18
2.4.6 Digital Adaptive Equalizer ....... 18
2.4.7 Auto-Negotiation ........................ 19
2.4.8 Smartspeed Function ................. 19
2.4.9 Automatic MDI/MDIX Crossover
19
2.4.10 Polarity Correction ..................... 19
2.5 Loopback Modes .................................... 19
2.5.1 Digital Loopback ......................... 19
2.5.2 External Cable Loopback ........... 19
2.5.3 Remote PHY Loopback .............. 20
2.6 Cable Diagnostic Test ............................ 20
2.7 Fiber Mode Support .............................. 20
2.7.1 IEEE 802.3 Remote Fault Indication
Support ......................................... 20
2.7.2 Fault Propagation ....................... 21
2.8 LED Interface .......................................... 21
2.9 Power Supplies ....................................... 22
2.10 Management Interface .......................... 24
2.11 Timing Sychronization ......................... 26
2.11.1 Synchronous Ethernet — Physical
Layer Timing Synchronization . 29
2.12 Atheros Green EthosTM ...................... 30
2.12.1 Low Power Modes ..................... 30
2.12.2 Shorter Cable Power Mode ....... 30
2.12.3 Hibernation Mode ...................... 30
2.13 IEEE 802.3az and Energy Efficient
Ethernet 30
2.14 IEEE 802.3az Energy Efficient Ethernet 30
2.14.1 IEEE 802.3az LPI Mode .............. 30
2.14.2 Atheros SmartEEE ...................... 31
2.15 Wake On LAN (WoL) .......................... 32
3 Electrical Characteristics ............33
3.1 Absolute Maximum Ratings ................ 33
3.2 Recommended Operating Conditions 33
3.3 RGMII Characteristics ........................... 34
3.4 SerDes and SGMII Characteristics ...... 37
3.5 MDIO Timing ......................................... 39
3.6 MDIO/MDC DC Characteristic .......... 39
3.7 Clock Characteristics ............................. 40
3.8 Power Pin Current Consumption ....... 41
3.9 Typical Power Consumption Parameters
41
3.10 Power-on Sequence, Reset and Clock 44
3.10.1 Power-on Sequence .................... 44
3.10.2 Reset and Clock Timing ............. 44
3.11 Digital Pin Design Guide ..................... 44
4 Register Descriptions ..................47
4.1 Register Summary ................................. 47
4.2 MII Registers .......................................... 47
4.2.1 Control Register — Copper Page 49
4.2.2 Control — Fiber Page ................. 50
4.2.3 Status Register — Copper Page 51
4.2.4 Status Register — Fiber Page .... 53
4.2.5 PHY Identifier ............................. 54
4.2.6 PHY Identifier2 ........................... 55
4.2.7 Auto-Negotiation Advertisement
Register — Copper Page ........... 55
4.2.8 Auto-Negotiation Advertisement
Register — Fiber Page ................ 57
4.2.9 Link Partner Ability Register —
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • 5
August 2011 • 5
5 Page 
Table 1-1. Signal to Pin Relationships and Descriptions
Symbol
MDI
TRXP0, TRXN0
TRXP1, TRXN1
TRXP2, TRXN2
TRXP3, TRXN3
RGMII
GTX_CLK
RX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
TX_EN
TXD0
TXD1
TXD2
TXD3
SGMII/1000FX
SIP/SIN
SOP/SON
SD
Pin Type Description
11, 12
14, 15
17, 18
20, 21
IA, OA
IA, OA
IA, OA
IA, OA
Media-dependent interface 0, differential 100 transmission line
Media-dependent interface 1, differential 100 transmission line
Media-dependent interface 2, differential 100 transmission line
Media-dependent interface 3, differential 100 transmission line
35 I, PD RGMII transmit clock, 125 MHz at 1000 Mbps, 25 MHz at 100
Mbps, and 2.5 MHz at 10 Mbps digital clock input
33 I/O, PD RGMII receive clock, 125 MHz at 1000 Mbps, 25 MHz at 100 Mbps,
and 2.5 MHz at 10 Mbps digital clock output
32 I/O, PD RGMII receive data valid
31 I/O, PD RGMII receive data 0
30 I/O, PD RGMII receive data 1
28 I/O, PD RGMII receive data 2
27 I/O, PD RGMII receive data 3
34 I, PD RGMII transmit enable
36 I, PD RGMII transmit data 0
37 I, PD RGMII transmit data 1
38 I, PD RGMII transmit data 2
39 I, PD RGMII transmit data 3
46, 45
43, 42
41
IA 1.25 Gbps transmit differential inputs
When this interface is used as a MAC interface, the MAC
transmitter's positive output connects to SIP and the MAC
transmitter's negative output connects to the SIN.
When this interface is used as a fiber interface, the fiber-optic
transceiver's positive output connects to the SIP and the fiber-optic
transceiver's negative output connects to the SIN.
OA 1.25 Gbps receive differential outputs
When this interface is used as a MAC interface, the MAC receiver's
positive input connects to SOP and the MAC receiver's negative
input connects to the SON.
When this interface is used as a fiber interface, the fiber-optic
transceiver's positive input connects to the SOP and the fiber-optic
transceiver's negative input connects to the SON.
IA Signal Detect. 1.2 V voltage level. Input signals must not exceed
1.4V.
Management Interface and Interrupt
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver • 11
August 2011 • 11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AR8031.PDF ] | |
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