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PDF FM24C16A Data sheet ( Hoja de datos )
| Número de pieza | FM24C16A | |
| Descripción | 16Kb FRAM Serial Memory | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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FM24C16A
16Kb FRAM Serial Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High Endurance (1012) Read/Write Cycles
• 45 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1MHz maximum bus frequency
• Direct hardware replacement for EEPROM
Description
The FM24C16A is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for over 45
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM24C16A performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
FM24C16A is capable of supporting 1012 read/write
cycles, or a million times more write cycles than
EEPROM.
These capabilities make the FM24C16A ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows the system to write
data more frequently, with less system overhead.
The FM24C16A provides substantial benefits to users
of serial EEPROM, and these benefits are available as
a hardware drop-in replacement. The FM24C16A is
available in an industry standard 8-pin SOIC and uses
a two-wire protocol. The specifications are
guaranteed over the industrial temperature range from
-40°C to +85°C.
Low Power Operation
• 5V operation
• 150 µA Active Current (100 kHz)
• 10 µA Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC (-S)
• “Green” 8-pin SOIC (-G)
Pin Configuration
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
SDA
SCL
WP
VDD
VSS
Function
Serial Data/Address
Serial Clock
Write Protect
Supply Voltage 5V
Ground
Ordering Information
FM24C16A-S 8-pin SOIC
FM24C16A-G “Green” 8-pin SOIC
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Mar. 2005
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 12
Free Datasheet http://www.datasheet4u.com/
1 page  
Slave ID
Page
Select
1 0 1 0 A2 A1 A0 R/W
Figure 4. Slave Address
Word Address
After the FM24C16A (as receiver) acknowledges the
slave ID, the master will place the word address on
the bus for a write operation. The word address is the
lower 8-bits of the address to be combined with the 3-
bits of the page select to specify the exact byte to be
written. The complete 11-bit address is latched
internally.
No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24C16A increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFh) is reached, the address latch will
roll over to 000h. There is no limit on the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24C16A can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24C16A will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
FM24C16A
Memory Operation
The FM24C16A is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C16A and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master sends
each byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 7FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ‘ready’ condition.
An actual memory array write occurs after the 8th data
bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8th data bit. The FM24C16A needs no page
buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24C16A will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.
Rev 3.0
Mar. 2005
Page 5 of 12
5 Page 
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
FM24C16A
Recommended PCB Footprint
Pin 1
4.90 ±0.10
3.90 ±0.10 6.00 ±0.20
1.35
1.75
2.00
1.27
0.25
0.50
7.70
3.70
0.65
45°
0.19
0.25
1.27 0.10
0.33 0.25
0.51
0.10 mm
0°- 8°
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXX-P
LLLLLLL
RICYYWW
Legend:
XXXX= part number, P= package type
LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24C16A, Standard SOIC package, Year 2004, Work Week 39
FM24C16A-S
A40003S
RIC0439
Rev 3.0
Mar. 2005
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FM24C16A.PDF ] | |
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