AD7960 Datasheet PDF - Analog Devices
| Part Number | AD7960 | |
| Description | 5 MSPS PulSAR Differential ADC | |
| Manufacturers | Analog Devices | |
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Data Sheet
FEATURES
Throughput: 5 MSPS
18-bit resolution with no missing codes
Excellent ac and dc performance
Dynamic range: 100 dB
SNR: 99 dB
THD: −117 dB
INL: ±0.8 LSB (typical), ±2 LSB (maximum)
DNL: ±0.5 LSB (typical), ±0.99 LSB (maximum)
True differential analog input voltage range: ±4.096 V or ±5 V
Low power dissipation
46.5 mW at 5 MSPS with external reference buffer
(echoed clock mode)
64.5 mW at 5 MSPS with internal reference buffer
(echoed clock mode)
39 mW at 5 MSPS with external reference buffer
(self clocked mode, CNV± in CMOS mode)
SAR architecture
No latency/pipeline delay
External reference options: 2.048 V buffered to 4.096 V (internal
reference buffer), 4.096 V, and 5 V
Serial LVDS interface
Self clocked mode
Echoed clock mode
LVDS or CMOS option for conversion control (CNV± signal)
Operating temperature range of −40°C to +85°C
32-lead, 5mm × 5mm LFCSP (QFN)
APPLICATIONS
Digital imaging systems
Digital X-rays
Computed tomography
IR cameras
MRI gradient control
High speed data acquisition
Spectroscopy
Test equipment
18-Bit, 5 MSPS PulSAR
Differential ADC
AD7960
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM VDD1 VDD2 VIO
IN+
IN–
AD7960
÷2 CLOCK
CAP
DAC
LOGIC
SAR
SERIAL
LVDS
EN0
EN1
EN2
EN3
CNV+, CNV–
D+, D–
DCO+, DCO–
CLK+, CLK–
GND
Figure 1.
GENERAL DESCRIPTION
The AD7960 is an 18-bit, 5 MSPS, charge redistribution successive
approximation (SAR), analog-to-digital converter (ADC). The
SAR architecture allows unmatched performance both in noise
and in linearity. The AD7960 contains a low power, high speed,
18-bit sampling ADC, an internal conversion clock, and an
internal reference buffer. On the CNV± edge, the AD7960
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and 4.096 V and between 0 V and 5 V. The reference voltage is
applied to the part externally. All conversion results are available
on a single LVDS self clocked or echoed clock serial interface.
The AD7960 is available in a 32-lead LFCSP (QFN) with
operation specified from −40°C to +85°C.
Table 1. Fast PulSAR® ADC Selection
Input Type
1 MSPS to 2 MSPS to
<2 MSPS 3 MSPS
Differential,1 AD7653
AD7985
16-Bit
AD7667
AD7980
AD7983
True Bipolar, AD7671
16-Bit
Differential,2
16-Bit
AD7677
AD7623
AD7621
AD7622
Differential,2 AD7643
AD7641
18-Bit
AD7982
AD7986
AD7984
5 MSPS
to 6 MSPS 10 MSPS
AD7625
AD7961
AD7960
AD7626
1 Ground sense.
2 Antiphase.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD7960
Parameter
Test Conditions/Comments Min Typ Max Unit
Converting: Internal Reference Buffer
Disabled
Echoed clock mode, CNV± in
LVDS mode
46.5 56.2 mW
Converting: Internal Reference Buffer
Enabled
Echoed clock mode, CNV± in
LVDS mode
64.5 76.4 mW
Converting: Internal Reference Buffer
Disabled
Self clocked mode, CNV± in
CMOS mode7
39 47.4 mW
Power-Down
EN3 to EN0 = X000
7.2 94.5 µW
Energy per Conversion
Self clocked, CNV± in CMOS
mode7
7.8 9.5 nJ/sample
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+85 °C
1 The minimum and maximum values are guaranteed by characterization.
2 Using an external reference.
3 See Table 8 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or
lower.
4 The REFIN pin is tied to 0 V in this mode.
5 The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV.
6 The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed.
7 CNV+ works as a CMOS input when CNV− is grounded. See Table 6 for additional information.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions
Acquisition Time
CNV± High Time
CNV± to D± (MSB) Ready
CNV± to Last CLK± (LSB) Delay
CLK± Period1
CLK± Frequency
CLK± to DCO± Delay (Echoed Clock Mode)
DCO± to D± Delay (Echoed Clock Mode)
CLK± to D± Delay
Symbol
tCYC
tACQ
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
tCLKD
Min Typ
Max
200
tCYC − 100
10 0.6 × tCYC
200
160
3.33 4
(tCYC − tMSB + tCLKL)/n
250 300
03
5
01
03
5
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
1 For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read, giving the maximum CLK±
frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 18; in self clocked interface mode, n = 20.
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