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부품번호 | CAV93C86 기능 |
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기능 | 16 Kb Microwire Serial EEPROM | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 9 페이지수
CAV93C86
16 Kb Microwire Serial
EEPROM
Description
The CAV93C86 is a 16 Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read) serially by
using the DI (or DO) pin. The CAV93C86 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin SOIC and TSSOP packages.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• High Speed Operation: 2 MHz
• Low Power CMOS Technology
• 2.5 V to 5.5 V Operation
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Hardware and Software Write Protection
• Power−up Inadvertent Write Protection
• Sequential Read
• Program Enable (PE) Pin
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• 8−pin SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
ORG
CS
SK
PE
CAV93C86
DI
DO
GND
Figure 1. Functional Symbol
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal pull−up device will
select the x16 organization.
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SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SK
DI
DO
VCC
PE
ORG
GND
SOIC (V) and TSSOP (Y)
Pin Name
CS
SK
DI
DO
VCC
GND
ORG
PE
PIN FUNCTION
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
Program Enable
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 0
1
Publication Order Number:
CAV93C86/D
Free Datasheet http://www.datasheet4u.com/
CAV93C86
Device Operation
The CAV93C86 is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAV93C86 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAV93C86 operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
Note: The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86 is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAV93C86 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C86 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
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4
4페이지 PIN # 1
IDENTIFICATION
TOP VIEW
CAV93C86
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
θ
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0º
NOM
1.27 BSC
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8º
D
A1
A
eb
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
h
θ
L
END VIEW
c
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7
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
CAV93C86 | 16 Kb Microwire Serial EEPROM | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |