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PDF PCA9617A Data sheet ( Hoja de datos )
| Número de pieza | PCA9617A | |
| Descripción | Level translating Fm I2C-bus repeater | |
| Fabricantes | NXP Semiconductors | |
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PCA9617A
Level translating Fm+ I2C-bus repeater
Rev. 1 — 20 March 2013
Product data sheet
1. General description
The PCA9617A is a CMOS integrated circuit that provides level shifting between low
voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus
or SMBus applications. While retaining all the operating modes and features of the
I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two
buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A
enables the system designer to isolate two halves of a bus for both voltage and
capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance
when the PCA9617A is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable
voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the
port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617A I/O drivers prevents them from being
connected to the static or incremented offset of other bus buffers. Port A of two or more
PCA9617As can be connected together, however, to allow a star topography with port A
on the common bus, and port A can be connected directly to any other buffer with static or
incremented offset outputs. Multiple PCA9617As can be connected in series, port A to
port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and
off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,
while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a latching condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
2. Features and benefits
2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of
the device at 1 MHz and up to 4000 pF at lower speeds
Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V
Footprint and functional replacement for PCA9517A at Fast-mode speeds
Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels
Free Datasheet http://www.datasheet4u.com/
1 page  
NXP Semiconductors
PCA9617A
Level translating Fm+ I2C-bus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9617A”.
The PCA9617A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.8 V
without degradation of system performance. The PCA9617A contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.8 V) and a 2.5 V, 3.3 V or 5 V I2C-bus or SMBus. All
inputs and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered
(VCC(B) and/or VCC(A) = 0 V). The PCA9617A includes a power-up circuit that keeps the
output drivers turned off until VCC(B) is above 2.2 V and until after the internal reference
circuits have settled ~400 s, and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be
applied in any sequence at power-up. After power-up and with the enable (EN) HIGH, a
LOW level on port A (below 0.3VCC(A)) turns the corresponding port B driver (either SDA
or SCL) on and drives port B down to about 0.55 V. When port A rises above 0.3VCC(A),
the port B pull-down driver is turned off and the external pull-up resistor pulls the pin
HIGH. When port B falls first and goes below 0.4 V, the port A driver is turned on and
port A pulls down to ~0 V. The port A pull-down is not enabled unless the port B voltage
goes below 0.4 V. If the port B low voltage goes below 0.4 V, the port B pull-down driver is
enabled and port B will only be able to rise to 0.55 V until port A rises above 0.3VCC(A),
then port B will continue to rise being pulled up by the external pull-up resistor. The VCC(A)
is only used to provide the 0.35VCC(A) reference to the port A input comparators and for
the power good detect circuit. The PCA9617A includes a VCC(A) overvoltage disable that
turns the channel off if 0.4VCC(A) + 0.8 V > VCC(B). The PCA9617A logic and all I/Os are
powered by the VCC(B) pin.
6.1 Enable
The EN pin is active HIGH with thresholds referenced to VCC(B) and an internal pull-up to
VCC(B) that maintains the device active unless the user selects to disable the repeater to
isolate a badly behaved slave on power-up until after the system power-up reset. It should
never change state during an I2C-bus operation because disabling during a bus operation
will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus
parts being enabled. The enable does not switch the internal reference circuits so the
~400 s delay is only seen when VCC(B) comes up.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode
and Fast-mode Plus I2C-bus devices in addition to SMBus devices. Standard mode and
Fast-mode I2C-bus devices only specify 3 mA output drive; this limits the termination
current to 3 mA in a generic I2C-bus system where Standard-mode devices, Fast-mode
devices and multiple masters are possible. When only Fast-mode Plus devices are used
with 30 mA at 5 V drive strength, then lower value pull-up resistors can be used. The
PCA9617A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
5 of 23
Free Datasheet http://www.datasheet4u.com/
5 Page 
NXP Semiconductors
PCA9617A
Level translating Fm+ I2C-bus repeater
Table 5. Static characteristics …continued
VCC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Typical values measured with VCC(A) = 0.95 V and VCC(B) = 2.5 V at 25 C, unless otherwise noted.
Symbol Parameter
Conditions
Min Typ Max
ILI input leakage current
1 - +1
Ci input capacitance
VI = VCC(B)
- 67
Unit
A
pF
[1] VCC(A) may be as high as 5.5 V for overvoltage tolerance but 0.4VCC(A) + 0.8 V VCC(B) for the channels to be enabled and functional
normally.
[2] For part to function, 0.4 VCC(A) must be equal or less than VCC(B) 0.8 V. The voltage on the A port can still be up to 5.5 V without
damage to the pins.
[3] Pull-up should result in IOL 150 A.
[4] Guaranteed by design and characterization.
[5] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
[6] When VCC(A) is less than 1 V, care is required to make certain that the system ground offset and noise are minimized such that there is
reasonable difference between the VIL present at the PCA9617A A-side input and the 0.25VCC(A) input threshold.
[7] Power supply decoupling capacitors need to be present for both VCC(A) and VCC(B) and the 0.1 F decoupling for VCC(B) needs to be
located near the VCC(B) pin.
0.70
port B VOL
(V)
0.65
0.60
VCC(B) = 2.2 V (Nom = 25 °C)
2.2 V (Hot = 85 °C)
3.0 V (Hot = 85 °C)
002aah461
0.4
Port A VOL
(V)
0.3
VCC(B) = 2.2 V (Nom = 25 °C)
2.2 V (Hot = 85 °C)
0.2
002aag896
0.55 0.1
0.50
0
10 20 30
port B IOL (mA)
Fig 10. Port B VOL versus IOL
0
0 10 20 30
Port A IOL (mA)
Fig 11. Port A VOL versus IOL
110
Port B
tPHL (ns)
100
002aag897
maximum
90 typical
minimum
80
70
50
100 150 200
CL at constant RC (pF)
RC = 67.5 ns, VCC(A) = 0.95 V, VCC(B) = 2.5 V, and Tamb = 25 C.
Fig 12. Nominal port B tPHL with load capacitance at constant RC
PCA9617A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
11 of 23
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PCA9617A.PDF ] | |
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