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PFS729EG 데이터시트 PDF




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부품번호 PFS729EG 기능
기능 (PFS704 - PFS729) High Power PFC Controller
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PFS729EG 데이터시트, 핀배열, 회로
PFS704-729EG
HiperPFSFamily
High Power PFC Controller with Integrated
High-Voltage MOSFET
Key Benefits
Single chip solution for boost power factor correction (PFC)
EN61000-3-2 Class C and D compliant
High light load efficiency at 10% and 20% load
>95% efficiency from 10% load to full load
<130 mW no-load consumption at 230 VAC with output in
regulation
<50 mW no-load consumption at 230 VAC in remote off state
Frequency adjusted over line voltage, and line cycle
Spread-spectrum across >60 kHz window to simplify EMI
filtering requirements
Lower boost inductance
Provides up to 1 kW peak output power
>1 kW peak power delivery in power limit voltage regulation
mode
High integration allows smaller form factor, higher power density
designs
Incorporates control, gate driver, and high-voltage power
MOSFET
Internal current sense reduces component count and system
losses
Protection features include: UV, OV, OTP, brown-in/out, cycle-
by-cycle current limit, and power limiting for overload protection
Halogen free and RoHS compliant
Applications
PC
Printer
LCD TV
Video game consoles
High power adaptors
High power LED lighting
Industrial and appliance
Generic PFC converters
Output Power Table
Product
Maximum Continuous
Output Power Rating at
90 VAC
Peak Output Power
Rating at 90 VAC
PFS704EG
110 W
120 W
PFS706EG
PFS708EG
PFS710EG
PFS712EG
PFS714EG
PFS716EG
140 W
190 W
240 W
300 W
350 W
388 W
150 W
205 W
260 W
320 W
385 W
425 W
Product
Maximum Continuous
Output Power Rating at
180 VAC
Peak Output Power
Rating at 180 VAC
PFS723EG
PFS724EG
PFS725EG
PFS726EG
PFS727EG
PFS728EG
PFS729EG
255 W
315 W
435 W
540 W
675 W
810 W
900 W
280 W
350 W
480 W
600 W
750 W
900 W
1000 W
Table 1. Output Power Table (see Notes on page 9)
+
VCC
DV
VCC
AC
IN
HiperPFS
CONTROL
FB
SG
DC
OUT
www.powerint.com
Figure 1. Typical Application Schematic.
PI-6021-110810
December 2011
Free Datasheet http://www.datasheet4u.com/




PFS729EG pdf, 반도체, 판매, 대치품
PFS704-729EG
Pin Functional Description
VOLTAGE MONITOR (V) Pin:
The V pin is tied to the rectified AC rail through an external
resistor. Internal circuitry detects the peak of the input line
voltage which resembles a full-wave rectified waveform. The
rectified high-voltage bus is connected directly to the V pin
voltage through a large resistor (4 MW for PFS70x and PFS71x;
9 MW for PFS72x) to minimize power dissipation and standby
power consumption. A small ceramic capacitor (0.1 mF for
PFS70x and PFS71x; 0.047 mF for PFS72x) is required from the
VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass
any switching noise present on the rectified bus. This pin also
features both brown-in and brown-out protection.
FEEDBACK (FB) Pin:
The FEEDBACK pin is high input-impedance reference terminal
that connects to a feedback resistor network. This pin will also
feature fast overvoltage and undervoltage detection circuitry
that will disengage the internal power MOSFET in the event of a
system fault. A 10 nF capacitor is required between the
FEEDBACK to SIGNAL GROUND pins; this capacitor must be
placed very close to the device on the PCB to bypass any
switching noise. This pin is also used for loop compensation.
BIAS POWER (VCC) Pin:
This is a 10-12 VDC bias supply used to power the IC. The bias
voltage must be externally clamped to prevent the VCC pin
from exceeding 13.4 VDC.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the G pin. The
SIGNAL GROUND pin must not be tied to the SOURCE pin.
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the tab and drain connection of the internal power switch.
E Package (eSIP-7G)
Exposed Metal (On Edge)
Internally Connected
to GROUND Pin
Exposed Metal
(On Edge)
Internally
Connected to
DRAIN Pin
1 23 45 7
Figure 2. Pin Configuration.
7 54 32 1
Exposed Pad
(Backside)
Internally
Connected to
DRAIN Pin
(see eSIP-7G
Package
Drawing)
PI-5334-083110
VOLTAGE MONITOR (V)
BIAS POWER (VCC)
INPUT
LINE INTERFACE
Peak
Detector
INTERNAL
SUPPLY
+
- VCC+
MON IVPK
Input UV
(IUV-/IUV+)
“Off-time derived with
6 V Input Voltage
Emulation
+
constant Volt-Sec
VO-VIN
- CINT
7 kHz
Filter
oVpOeFFraitsinagffurnecqtuioenncoyf tahseaefruronrc-tvioonltaogfeo(uVtpEu) tapnodwiserufsoerdintcorereadsuecdeetfhfieciaevnecryage
(PFS704-716).
(VOFF = 0.8 V for PFS723-729).
IVPK
Frequency
Slide
FEEDBACK (FB)
Internal
Reference
Transconductance
Error-Amplifier
VREF
+
1 kHz
Filter
-
VE
MseOnNsies
the switch current
scale factor which
is function of peak line
FBOV
+
- Fast OV
FFBBOUFVF/
Comparator
+
voltage derived from IVIN
MON IS
- UV Comparator
VOFF
Comparator
-
+
Latch
VE
Comparator
+
-
TIMER
SUPERVISOR
Input UV
FBOV/UV
OTP
The
internal derived error-voltage
regulates the output voltage
(VE)
CINT
SIGNAL GROUND (G)
Figure 3. Functional Block Diagram.
4
Rev. D 12/11
DRAIN (D)
OTP
SOFT
START
VCC
Sense
FET
Driver
LEB
IS
Power
MOSFET
OCP
+
-
IOCP
SOURCE (S)
PI-5333-113010
www.powerint.com
Free Datasheet http://www.datasheet4u.com/

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PFS729EG 전자부품, 판매, 대치품
PFS704-729EG
120
110
230 VAC
100
90
80
70
60
50
40
30
20
10 Peak Load
0
180 VAC 135 VAC 115 VAC
90 VAC
45 90 135
Line Conduction Angle (°C)
180
120
110
VIN = 115 VAC
100
90
80
70
60
50
40
30
20
10
0
45
100% Peak Load
Expected Frequency
Range at Peak
Rated Load
75% Peak Load
50% Peak Load
25% Peak Load
90 135 180
Line Conduction Angle (°C)
Figure 8. (a) Frequency Variation Over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation Over Line Half-Cycle as a Function of Load.
~5 V
~5 V
~2.5 V
PFS704-716
VIN > 170 VAC
PFS704-716
VIN < 140 VAC
~1.25 V
~2.5 V
PFS704-716
~0.8 V
PFS723-729
~4.8 V
~5 V
VE (full power)
~140 VAC
~170 VAC
VIN PI-5338-021711
Figure 9. VOFF vs. VE and VOFF vs. Input Voltage.
controlled with respect to the internal error-voltage level (output
power) to allow the converter to maintain output voltage
regulation and relatively flat conversion efficiency between 10%
to 100% of rated load which is essential to meet many efficiency
directives.
The degree of frequency slide is also controlled as a function of
peak input line voltage, at high input line the maximum off-time
voltage reference at zero error-voltage will be approximately 1/2
of the maximum value at low input line conditions.
ThhigehloinwpeurtVliOnFeF
slope reduces
operation.
the
average
frequency
swing
for
Protection Modes
VOLTAGE MONITOR (V) Pin Shutdown
The VOLTAGE MONITOR pin features a shutdown protection
mode which can be used with the VOLTAGE MONITOR pin
resistor or external circuitry to cover system faults. During
start-up (1 V < VFB < 5.8 V) in the event the current through the
VOLTAGE MONITOR pin exceeds the IV(OFF) threshold for a
duration exceeding approximately (1 ms), the IC disables the
internal MOSFET for the entire duration that the V pin current is
apthbineoeIvCxecwIeV(iOellFdFr)se. intIhniteianItoVe(rOmFthF)aetlhsortepaserhtr-aoutlpidonsfo,erqifauthedenuccraeut.riorennet xthcreoeudginhgthtVe(OVFF),
BThroewVnO-LITnAPGrEotMecOtNioInTO(IRUV+p)in features an input line undervoltage
detection to limit the minimum start-up voltage detected
through the V pin. This detection threshold will inhibit the
device from starting at very low input AC voltage.
TBhroewVnp-iOn ufetaPturoretsecatibornow(InUV--o) ut protection mode wherein the
HiperPFS will turn-off when the V pin current is below the Line
UV-threshold for a period
the event a single half-line
ecxycceleedisinmgisthseintgRE(FnRoESrHmtiaml eoppeerraiotidng.
In
line frequency is 47 to 63 Hz) the brown-out protection will not
be activated. The HiperPFS shutdown in effect gradually
reduces the internal error-voltage to zero volts at rate of 1 V/ms
www.powerint.com
7
Rev. D 12/11
Free Datasheet http://www.datasheet4u.com/

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PFS729EG

(PFS704 - PFS729) High Power PFC Controller

Power Integrations
Power Integrations

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