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Número de pieza RJK0230DPA
Descripción Silicon N Channel Power MOS FET
Fabricantes Renesas 
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Preliminary Datasheet
RJK0230DPA
Silicon N Channel Power MOS FET with Schottky Barrier Diode
High Speed Power Switching
R07DS0541EJ0110
Rev.1.10
Sep 12, 2011
Features
Low on-resistance
Capable of 4.5 V gate drive
High density mounting
Pb-free
Halogen-free
Outline
RENESAS Package code: PWSN0008DD-B
(Package name: WPAK-D(3))
5 678
1
G1
234
D1 D1 D1
8
G2
4 32 1
MOS1
9
S1/D2
5678
9
S2 S2 S2
56 7
4321
(Bottom View)
MOS2 and
Schottky Barrier Diode
1, 8 Gate
2, 3, 4, 9 Drain
5, 6, 7, 9 Source
Absolute Maximum Ratings
Item
Symbol
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
VDSS
VGSS
ID
ID(pulse)Note1
IDR
IAP Note 2
EAR Note 2
Pch Note3
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. PW 10 s, duty cycle 1%
2. Value at Tch = 25C, Rg 50 
3. Tc=25C
MOS1
25
±20
20
80
20
12
18
15
150
–55 to +150
Ratings
MOS2
25
±12
50
200
50
23
66
35
150
–55 to +150
(Ta = 25°C)
Unit
V
V
A
A
A
A
mJ
W
°C
°C
R07DS0541EJ0110 Rev.1.10
Sep 12, 2011
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RJK0230DPA pdf
RJK0230DPA
Static Drain to Source On State Resistance
vs. Temperature
20
Pulse Test
16
ID = 2 A, 5 A, 10 A
12
VGS = 4.5 V
8
4 10 V
2 A, 5 A, 10 A
0
–25 0 25 50 75 100 125 150
Case Temperature Tc (°C)
Dynamic Input Characteristics
50
ID = 20 A
40
30
VDD = 20 V
10 V
20
VGS
16
12
VDS
20
8
10 4
VDD = 20 V
10 V
00
0 6 12 18 24 30
Gate Charge Qg (nc)
Maximum Avalanche Energy vs.
Channel Temperature Derating
20
16
12
8
4
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Preliminary
10000
Typical Capacitance vs.
Drain to Source Voltage
3000
1000
Ciss
300
100
30
VGS = 0
10 f = 1 MHz
0
10
Coss
Crss
20 25
Drain to Source Voltage VDS (V)
Reverse Drain Current vs.
Source to Drain Voltage
50
10 V
Pulse Test
5V
40
30
20
10 VGS = 0, –5 V
0 0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage VSD (V)
R07DS0541EJ0110 Rev.1.10
Sep 12, 2011
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RJK0230DPA arduino
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