|
|
PDF CYUSB3011 Data sheet ( Hoja de datos )
| Número de pieza | CYUSB3011 | |
| Descripción | FX3 SuperSpeed USB Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CYUSB3011 (archivo pdf) en la parte inferior de esta página. Total 40 Páginas | ||
|
No Preview Available !
CYUSB301X
EZ-USB® FX3 SuperSpeed USB Controller
Features
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0
specification 1.0
❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐ 8-, 16-, and 32-bit data bus
❐ As many as16 configurable control signals
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Additional connectivity to the following peripherals
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
Logic Block Diagram
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V
■ 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
package
■ EZ-USB® software and development kit (DVK) for easy code
development
Applications
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Scanners
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Portable media players
■ Industrial cameras
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
DQ[31 : 0]/
DQ[15 : 0]
CTL[12:0]
PMODE[2:0]
INT#
RESET #
GPIF™ II
I2C
JTAG
ARM926EJ -S
UART
SPI
Embedded
SRAm
(512 kB/
256 KB)
32
EPs
I2S
HS/FS/ LS
OTG Host
SS
Peripheral
HS/FS
Peripheral
EZ-Dtect™
OTG_ID
SSRX -
SSRX +
SSTX -
SSTX +
D+
D-
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-52136 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 16, 2012
Free Datasheet http://www.datasheet4u.com/
1 page  
CYUSB301X
OTG Connectivity
In OTG mode, FX3 can be configured to be an A, B, or dual-role
device. It can connect to the following:
■ ACA device
■ Targeted USB peripheral
■ SRP-capable USB peripheral
■ HNP-capable USB peripheral
■ OTG host
■ HNP-capable host
■ OTG device
ReNumeration
Because of FX3's soft configuration, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into USB, FX3 enumerates automatically with
the Cypress Vendor ID (0x04B4) and downloads firmware and
USB descriptors over the USB interface. The downloaded
firmware executes an electrical disconnect and connect. FX3
enumerates again, this time as a device defined by the
downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is plugged in.
EZ-Dtect
FX3 supports USB Charger and accessory detection (EZ-Dtect).
The charger detection mechanism complies with the Battery
Charging Specification Revision 1.1. In addition to supporting
this version of the specification, FX3 also provides hardware
support to detect the resistance values on the ID pin.
FX3 can detect the following resistance ranges:
■ Less than 10 Ω
■ Less than 1 kΩ
■ 65 kΩ to 72 kΩ
■ 35 kΩ to 39 kΩ
■ 99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)
■ 119 kΩ to 132 kΩ
■ Higher than 220 kΩ
■ 431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)
FX3's charger detects a dedicated wall charger, Host/Hub
charger, and Host/Hub.
VBUS Overvoltage Protection
The maximum input voltage on FX3's VBUS pin is 6 V. A charger
can supply up to 9 V on VBUS. In this case, an external
overvoltage protection (OVP) device is required to protect FX3
from damage on VBUS. Figure 4 shows the system application
diagram with an OVP device connected on VBUS. Refer to
Table 7 for the operating range of VBUS and VBATT.
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
1 OVP device
2
3
4
5
6
7
8
9 GND
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
EZ-USB FX3
Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over
D+/D–) for non-USB serial data transfer. This mode is based on
the CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V.
When configured for the Carkit UART mode, TXD of UART
(output) is mapped to the D– line, and RXD of UART (input) is
mapped to the D+ line.
In the Carkit UART mode, FX3 disables the USB transceiver and
D+ and D– pins serve as pass-through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49], as
shown in Figure 5 on page 6.
In this mode, FX3 supports a rate of up to 9600 bps.
Document Number: 001-52136 Rev. *L
Page 5 of 40
Free Datasheet http://www.datasheet4u.com/
5 Page 
CYUSB301X
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low-Power Mode
Characteristics
Methods of Entry
Methods of Exit
Standby Mode (L3)
■ The power consumption in this mode does ■ Firmware executing on
■ Detection of VBUS
not exceed ISB3
■ All configuration register settings and
program/data RAM contents are
ARM926EJ-S core or external
processor configures the appropriate
register
■ Level detect on
UART_CTS (Program-
mable Polarity)
preserved. However, data in the buffers or
other parts of the data path, if any, is not
guaranteed. Therefore, the external
■ GPIF II interface
assertion of CTL[0]
processor should take care that the data
needed is read before putting FX3 into this
■ Assertion of RESET#
Standby Mode
■ The program counter is reset after waking
up from Standby
■ GPIO pins maintain their configuration
■ Crystal oscillator is turned off
■ Internal PLL is turned off
■ USB transceiver is turned off
■ ARM926EJ-S core is powered down.
Upon wakeup, the core re-starts and runs
the program stored in the program/data
RAM
Core Power Down
Mode (L4)
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
■ The power consumption in this mode does ■ Turn off VDD
not exceed ISB4
■ Core power is turned off
■ Reapply VDD
■ Assertion of RESET#
■ All buffer memory, configuration registers,
and the program RAM do not maintain
state. After exiting this mode, reload the
firmware
■ In this mode, all other power domains can
be turned on/off individually
Document Number: 001-52136 Rev. *L
Page 11 of 40
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet CYUSB3011.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CYUSB3011 | FX3 SuperSpeed USB Controller | Cypress Semiconductor |
| CYUSB3012 | FX3 SuperSpeed USB Controller | Cypress Semiconductor |
| CYUSB3013 | FX3 SuperSpeed USB Controller | Cypress Semiconductor |
| CYUSB3014 | FX3 SuperSpeed USB Controller | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |