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PDF BD9673EFJ Data sheet ( Hoja de datos )
| Número de pieza | BD9673EFJ | |
| Descripción | Flexible Step-down Switching Regulator | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Single-chip Type with Built-in FET Switching Regulators
Flexible Step-down
Switching Regulator
with Built-in Power MOSFET
BD9673EFJ
No.11027EBT57
●Description
Output 1.5A and below High Efficiency Rate Step-down Switching Regulator Power MOSFET Internal Type BD9673EFJ
mainly used as secondary side Power supply, for example from fixed Power supply of 12V, 24V etc, Step-down Output of
1.2V/1.8V/3.3V/5V, etc, can be produced. This IC has external Coil/Capacitor down-sizing through 300 kHz Frequency
operation, inside Nch-FET SW for 45V “withstand-pressure” commutation and also, high speed load response through
Current Mode Control is a simple external setting phase compensation system, through a wide range external constant, a
compact Power supply can be produced easily.
●Features
1) Internal 200 mΩ Nch MOSFET
2) Output Current 1.5A
3) Oscillation Frequency 300kHz
4) Synchronizes to External Clock ( 200kHz～500kHz )
5) Feedback Voltage 1.0V±1.0%
6) Internal Soft Start Function
7) Internal Over Current Protect Circuit, Low Input Error Prevention Circuit, Heat Protect Circuit
8) ON/OFF Control through EN Pin (Standby Current 0 A Typ.)
9) Package: HTSOP-J8 Package
●Applications
For Household machines in general that have 12V/24V Lines, etc.
●Absolute Maximum Rating
Parameter
Symbol
Ratings
Unit
VCC-GND Supply Voltage
VCC
45
V
BST-GND Voltage
VBST
50
V
BST-Lx Voltage
⊿VBST
7
V
EN-GND Voltage
VEN
45
V
Lx-GND Voltage
VLX 45 V
FB-GND Voltage
VFB 7 V
VC-GND Voltage
VC 7 V
SYNC-GND Voltage
SYNC
7
V
High-side FET Drain Current
IDH
2.0
A
Power Dissipation
Pd
3.76(*1)
W
Operating Temperature
Topr -40～+105 ℃
Storage Temperature
Tstg -55～+150 ℃
Junction Temperature
Tjmax
+150
℃
(*1)During mounting of 70×70×1.6t mm 4layer board (Copper area:70mm×70mm).Reduce by 30.08mW for every 1℃ increase. (Above 25℃)
●Operating Conditions (Ta=25℃)
Parameter
Power Supply Voltage
Output Voltage
(*2)Restricted by minimum on pulse typ. 200ns
Symbol
VCC
VOUT
Min.
7
1.0(*2)
Ratings
Typ.
－
－
Max.
42
VCC×0.7
Unit
V
V
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
1/16
2011.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
1 page  
BD9673EFJ
Technical Note
●Detailed Description
◇Synchronizes to External Clock
The SYNC pin can be used to synchronize the regulator to an external system clock. To implement the synchronization
feature connect a square wave to SYNC pin. The square wave amplitude must transition lower than 0.8V and higher than
2.0V on the SYNC pin and have an on time greater than 100 ns and an off time greater than 100 ns. The synchronization
frequency range is 200 kHz to 500 kHz. The rising edge of the LX will be synchronized to the falling edge of SYNC pin
signal after SYNC input pulse 3 count. At the synchronization, the external clock is removed, the device transitions
self-running mode after 7 microseconds.
SYNC
SYNC_LATCH
Lx
Set the latch for
synchronization
400nsec
about
7µsec
Fig.3 Timing chart at Synchronization
◇SOFT START
The soft start time of BD9763EFJ is determined by the DCDC operating frequency (self-run mode 300 kHz ⇒10ms).
If synchronization is used at the time of EN=ON, The soft start time is restricted by SYNC pin input pulse frequency.
SYNC pin input pulse frequency is fosc_ex kHz, the soft start time is expressed by below equation.
300
Tss = fosc_ex
× 10 [ms]
◇OCP operation
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13msec restart.
VC
Lx
VOUT
OCP threshold
VC voltage rising by
output connect to GND
VC voltage discharged
by OCP latch
force the High side FET OFF
by detecting OCP current
(pulse by pulse protection)
output connect to GND
OCP
OCP_LATCH
set the OCP latch by detecting
the OCP current 2 times sequencially
OCP latch reset after 13 msec
(300ｋHz 4000 counts)
Fig.4 Timing chart at OCP operation
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
5/16
2011.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
5 Page 
BD9673EFJ
Technical Note
(5) About Adjustment of DC/DC Comparator Frequency Characteristics
Role of Phase compensation element CC1, CC2, RC (See P.7 Example of Reference Application Circuit)
Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.
The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of
resistor and capacitor that are connected in series to the VC Pin.
DC Gain of Voltage Return Loop can be calculated for using the following formula.
Adc
= Rl Gcs
AEA
V FB
Vout
Here, VFB is Feedback Voltage (1.0V).AEA is Voltage Gain of Error amplifier (typ : 77dB), Gcs is the Trans-conductance
of Current Detect (typ : 10A/V), and Rl is the Output Load Resistance value.
There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.
fp1 =
G EA
2π C1 A EA
fp2 =
1
2π COUT Rl
Here, GEA is the trans-conductance of Error amplifier(typ : 220µA/V).
Here, in this Control Loop, one zero becomes important.
With the zero which occurs because of Phase compensation Capacitor C1 and Phase compensation Resistor R3, the
Frequency below appears.
1
fz 1 =
2π C1 R3
Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an
important, separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.
fz
=
1
2π COUT
RESR
(ESR zero)
In this case, the 3rd pole determined with the 2nd Phase compensation Capacitor (C2) and Phase Correction Resistor
(R3) is used in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.
fp 3 =
1
2π C2 R3
(pole that corrects ESR zero)
The target of Phase compensation design is to create a communication function in order to acquire necessary band
and Phase margin.
Cross-over Frequency (band) at which Loop gain of Return Loop becomes “0” is important.
When Cross-over Frequency becomes low, Power supply Fluctuation Response, Load Response, etc worsens.
On the other hand, when Cross-over Frequency is too high, instability of the Loop can occur.
Tentatively, Cross-over Frequency is targeted to be made 1/20 or below of Switching Frequency.
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
11/16
2011.07 - Rev.B
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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