PDF ADIS16266 Data sheet ( Hoja de datos )

Número de pieza	ADIS16266
Descripción	Digital Gyroscope Sensor
Fabricantes	Analog Devices
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Data Sheet ±14,000°/sec Digital Gyroscope Sensor ADIS16266 FEATURES GENERAL DESCRIPTION Yaw rate gyroscope with range scaling The ADIS16266 is a programmable digital gyroscope that combines ±3500°/sec, ±7000°/sec, and ±14,000°/sec settings industry-leading MEMS and signal processing technology in a 2429 SPS sample rate Wide sensor bandwidth: 360 Hz No external configuration required to start data collection Start-up time: 170 ms Sleep mode recovery time: 2.5 ms Factory-calibrated sensitivity and bias Calibration temperature range: −40°C to +70°C SPI-compatible serial interface Relative angle displacement output Embedded temperature sensor Programmable operation and control Automatic and manual bias correction controls Bartlett window FIR filter length, number of taps Digital I/O: data ready, alarm indicator, general-purpose Alarms for condition monitoring Sleep mode for power management DAC output voltage Single-command self-test Single-supply operation: 4.75 V to 5.25 V single compact package. It provides accuracy performance that requires full motion calibration with any other MEMS gyroscope in this class. When power is applied, the ADIS16266 automatically starts up and begins sampling sensor data, without requiring configuration commands from a system processor. An addressable register structure and a common serial peripheral interface (SPI) provide simple access to sensor data and configuration settings. Many digital processor platforms support the SPI with simple firmware level instructions. The ADIS16266 provides several programmable features for in-system optimization. The Bartlett window FIR filter length and sample rate settings provide users with controls that enable noise vs. bandwidth optimization. The digital input/output lines offer options for a data ready signal that helps the master processor efficiently manage data coherency, an alarm indicator signal for triggering master processor interrupts, and a general-purpose function for setting and monitoring system level digital controls/ conditions. 3.3 V compatible digital lines The ADIS16266 is pin-compatible with the ADIS1625x and 2000 g shock survivability ADIS1626x families and comes in an LGA package (11.2 mm × Operating temperature range: −40°C to +105°C 11.2 mm × 5.5 mm) that meets Pb-free solder reflow profile APPLICATIONS Platform control and stabilization requirements, per JEDEC J-STD-020. It offers an extended operating temperature range of −40°C to +105°C. Navigation Medical instrumentation Robotics FUNCTIONAL BLOCK DIAGRAM DIO1 DIO2 RST VCC RATE FILT MEMS GYROSCOPE SENSOR AUX ADC VREF AUX DAC TEMPERATURE SENSOR POWER SUPPLY ADIS16266 SELF-TEST INPUT/ OUTPUT ALARMS POWER MANAGEMENT GND CONTROLLER USER CONTROL REGISTERS CLOCK FILTER CALIBRATION OUTPUT DATA REGISTERS SPI PORT Figure 1. CS SCLK DIN DOUT Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Free Datasheet http://www.datasheet4u.com/ 1 page Data Sheet ADIS16266 TIMING SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted. Table 2. Parameter fSCLK tDATARATE tSTALL tCS tDAV tDSU tDHD tDF tDR tSFS Description Serial clock (not shown in figures) Data rate period Stall period between data Chip select to clock edge Data output valid after SCLK falling edge2 Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time (not shown in figures) Data output rise time (not shown in figures) CS high after SCLK edge3 Min 1 0.01 32 9 48.8 24.4 48.8 5 Typ 5 5 Max1 2.5 100 12.5 12.5 Unit MHz µs µs ns ns ns ns ns ns ns 1 Guaranteed by design; not production tested. 2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The remaining DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line enters a high impedance state. Timing Diagrams tDATARATE CS SCLK tSTALL Figure 2. SPI Chip Select Timing CS SCLK DOUT DIN tCS 1 * MSB R/W 23 4 5 6 tDAV DB14 tDSU DB13 DB12 tDHD DB11 DB10 A5 A4 A3 A2 15 16 tSFS DB2 DB1 LSB D2 D1 LSB *NOT DEFINED Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1) Rev. 0 \| Page 5 of 24 Free Datasheet http://www.datasheet4u.com/ 5 Page Data Sheet ADIS16266 USER REGISTERS Table 7. User Register Memory Map Name R/W Flash Backup FLASH_CNT R Yes SUPPLY_OUT R No GYRO_OUT R No GYRO_OUT2 R No Reserved N/A2 N/A2 AUX_ADC R No TEMP_OUT R No Reserved N/A2 N/A2 GYRO_OFF R/W Yes GYRO_SCALE R/W Yes Reserved N/A2 N/A2 ALM_MAG1 R/W Yes ALM_MAG2 R/W Yes ALM_SMPL1 R/W Yes ALM_SMPL2 R/W Yes ALM_CTRL R/W Yes Reserved N/A2 N/A2 AUX_DAC R/W No GPIO_CTRL R/W No MSC_CTRL R/W Yes SMPL_PRD R/W Yes SENS_AVG R/W Yes SLP_CNT W Yes DIAG_STAT R No GLOB_CMD W No LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM R R R R Yes Yes Yes Yes Address1 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0F to 0x13 0x14 0x16 0x18 to 0x1F 0x20 0x22 0x24 0x26 0x28 0x2B to 0x2F 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 to 0x51 0x52 0x54 0x56 0x58 Default N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 0x0000 0x0800 N/A2 0x0000 0x0000 0x0000 0x0000 0x0000 N/A2 0x0000 0x0000 0x0006 0x0000 0x0401 N/A2 N/A2 N/A2 N/A2 N/A N/A2 0x3F8A N/A2 Register Description Flash memory write count Output, power supply Output, gyroscope Output, gyroscope, bit growth from decimation Reserved Output, auxiliary ADC measurement Output, temperature (internal) Reserved Gyroscope bias correction Gyroscope scale correction Reserved Alarm 1 trigger setting Alarm 2 trigger setting Alarm 1 sample period Alarm 2 sample period Alarm configuration Reserved Control, DAC output voltage setting Control, digital I/O line Control, data ready, self-test settings Control, internal sample rate Control, dynamic range, filtering Control, sleep mode initiation Diagnostic, error flags Control, global commands Reserved Lot Identification Code 1 Lot Identification Code 2 Product identifier; 16,266 Serial number Bit Descriptions See Table 27 See Table 13 See Table 8 See Table 10 See Table 15 See Table 11 See Table 19 See Table 20 See Table 30 See Table 31 See Table 32 See Table 33 See Table 34 See Table 25 See Table 23 See Table 24 See Table 17 See Table 18 See Table 22 See Table 29 See Table 21 See Table 37 See Table 37 See Table 37 See Table 37 1 Each register contains two bytes. The address column in this table only offers the address of the lower byte. Add 1 to it to calculate the address of the upper byte. 2 N/A means not applicable. Rev. 0 \| Page 11 of 24 Free Datasheet http://www.datasheet4u.com/ 11 Page

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