DataSheet.es    


PDF IT8511TE Data sheet ( Hoja de datos )

Número de pieza IT8511TE
Descripción Embedded Controller
Fabricantes ITE　
Logotipo ITE Logotipo



Hay una vista previa y un enlace de descarga de IT8511TE (archivo pdf) en la parte inferior de esta página.


Total 70 Páginas

No Preview Available ! IT8511TE Hoja de datos, Descripción, Manual

IT8511E/TE/G
Embedded Controller
Preliminary Specification 0.4.1
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
Free Datasheet http://www.datasheet4u.com/

1 page




IT8511TE pdf
IT8511E/TE/G
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 48
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 48
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 48
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 48
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 48
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 48
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 49
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 49
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 49
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 49
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 49
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 50
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 50
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 50
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 50
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 50
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 50
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 51
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 51
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 51
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 51
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 52
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 52
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 52
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 52
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 52
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 52
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 53
6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 53
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 53
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 54
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 54
6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 54
6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 55
6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 55
6.2.8.11 P80L Begin Index (P80LB) ...................................................................................... 55
6.2.8.12 P80L End Index (P80LE)......................................................................................... 55
6.2.8.13 P80L Current Index (P80LC) ................................................................................... 55
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 56
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 56
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 56
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 57
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 57
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 57
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 57
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58
www.ite.com.tw
ii IT8511E/TE/G V0.4.1
Free Datasheet http://www.datasheet4u.com/

5 Page





IT8511TE arduino
IT8511E/TE/G
7.3.4 EC Interface Registers ....................................................................................................... 168
7.3.4.1 Wake-Up Edge Mode Register (WUEMR1) .......................................................... 168
7.3.4.2 Wake-Up Edge Mode Register (WUEMR2) .......................................................... 169
7.3.4.3 Wake-Up Edge Mode Register (WUEMR3) .......................................................... 169
7.3.4.4 Wake-Up Edge Mode Register (WUEMR4) .......................................................... 169
7.3.4.5 Wake-Up Edge Sense Register (WUESR1).......................................................... 169
7.3.4.6 Wake-Up Edge Sense Register (WUESR2).......................................................... 170
7.3.4.7 Wake-Up Edge Sense Register (WUESR3).......................................................... 170
7.3.4.8 Wake-Up Edge Sense Register (WUESR4).......................................................... 170
7.3.4.9 Wake-Up Enable Register (WUENR1) .................................................................. 171
7.3.4.10 Wake-Up Enable Register (WUENR2) .................................................................. 171
7.3.4.11 Wake-Up Enable Register (WUENR3) .................................................................. 171
7.3.4.12 Wake-Up Enable Register (WUENR4) .................................................................. 171
7.3.5 WUC Input Assignments .................................................................................................... 172
7.3.6 Programming Guide ........................................................................................................... 173
7.4 Keyboard Matrix Scan Controller .................................................................................................... 174
7.4.1 Overview............................................................................................................................. 174
7.4.2 Features ............................................................................................................................. 174
7.4.3 EC Interface Registers ....................................................................................................... 174
7.4.3.1 Keyboard Scan Out Low Byte Data Register (KSOL) ........................................... 174
7.4.3.2 Keyboard Scan Out High Byte Data 1 Register (KSOH1)..................................... 174
7.4.3.3 Keyboard Scan Out Control Register (KSOCTRL)................................................ 174
7.4.3.4 Keyboard Scan Out High Byte Data 2 Register (KSOH2)..................................... 175
7.4.3.5 Keyboard Scan In Data Register (KSIR) ............................................................... 175
7.4.3.6 Keyboard Scan In Control Register (KSICTRLR).................................................. 175
7.5 General Purpose I/O Port (GPIO) ................................................................................................... 176
7.5.1 Overview............................................................................................................................. 176
7.5.2 Features ............................................................................................................................. 176
7.5.3 EC Interface Registers ....................................................................................................... 176
7.5.3.1 General Control Register (GCR) ........................................................................... 176
7.5.3.2 Port Data Registers A-M (GPDRA-GPDRM)......................................................... 177
7.5.3.3 Port Data Mirror Registers A-M (GPDMRA-GPDMRM) ........................................ 177
7.5.3.4 Port Control n Registers (GPCRn, n = A0-I7)........................................................ 178
7.5.3.5 Output Type Registers A-I (GPOTA-GPOTI)......................................................... 180
7.5.4 Alternate Function Selection .............................................................................................. 181
7.5.5 Programming Guide ........................................................................................................... 186
7.6 EC Clock and Power Management Controller (ECPM) .................................................................. 187
7.6.1 Overview............................................................................................................................. 187
7.6.2 Features ............................................................................................................................. 187
7.6.3 EC Interface Registers ....................................................................................................... 187
7.6.3.1 Clock Frequency Select Register (CFSELR) ........................................................ 187
7.6.3.2 Clock Gating Control 1 Register (CGCTRL1R) ..................................................... 187
7.6.3.3 Clock Gating Control 2 Register (CGCTRL2R) ..................................................... 188
7.6.3.4 Clock Gating Control 3 Register (CGCTRL3R) ..................................................... 189
7.6.3.5 PLL Control (PLLCTRL) ........................................................................................ 189
7.6.3.6 Auto Clock Gating (AUTOCG)............................................................................... 189
7.7 SM Bus Interface (SMB) ................................................................................................................. 191
7.7.1 Overview............................................................................................................................. 191
7.7.2 Features ............................................................................................................................. 191
7.7.3 Functional Description........................................................................................................ 191
7.7.3.1 SMBUS Master Interface....................................................................................... 191
7.7.3.2 SMBUS Porting Guide ........................................................................................... 192
7.7.4 EC Interface Registers ....................................................................................................... 196
7.7.4.1 Host Status Register (HOSTA).............................................................................. 196
7.7.4.2 Host Control Register (HOCTL)............................................................................. 197
7.7.4.3 Host Command Register (HOCMD) ...................................................................... 198
www.ite.com.tw
viii IT8511E/TE/G V0.4.1
Free Datasheet http://www.datasheet4u.com/

11 Page







PáginasTotal 70 Páginas
PDF Descargar[ Datasheet IT8511TE.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IT8511TEEmbedded ControllerITE
ITE

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar